Cadence Design Systems, Inc.

Other

Proplus Design Solutions, Inc.

Primarius Technologies Co., Ltd.

Yutao Ma

Zhihong Liu

Bruce W McGaughy

Lifeng Wu

Yi Xu

Min-Chie Jeng

Min-Che Jeng

Method and System for Parallel Design and Technology Optimization are disclosed. The disclosed method enables efficient parallel design and technology optimization (PDTO) and allow designers to sign off the technology development or find the optimal design point with the design analysis tools. The method includes generating, from a manufacturing technology process, a baseline SPICE model based on technology specification and manufacturing process data; extending the baseline SPICE model to a corresponding description of technology specification window in the circuit design process, where the technology specification window describes extended ranges of device model parameters; extracting a targeted SPICE model using the technology specification window; verifying, by a circuit design process that operates in parallel to the manufacturing technology process, the integrated circuit meets a design specification using the targeted SPICE model.

Method and system for parallel design and technology optimization

Methods and systems are disclosed for determining a yield of a circuit in semiconductor manufacturing. In one embodiment, a computer implemented method includes performing a first pass of Monte Carlo simulations of the circuit to identify a plurality of failed sampling points in a high sigma region of a statistical distribution, partitioning the plurality of failed sampling points into a plurality of clusters based on angular separation of the plurality of failed sampling points, determining a boundary of each cluster in the plurality of clusters, performing sensitivity analysis from the boundary of the each cluster to identify an estimated closest failed sampling point associated with the each cluster, and performing a second pass of Monte Carlo simulations of the circuit to determine the yield of the circuit using the estimated closest failed sampling point associated with the each cluster and the boundary of each cluster in the plurality of clusters.

Adaptive high sigma yield prediction

Model evaluation and circuit simulation/verification is performed in a graphical processing unit (GPU). A multitude of first texture data corresponding to size parameters of devices are stored. A multitude of second texture data corresponding to instance parameters of the devices are stored. A multitude of third texture data corresponding to models of the devices are stored. A multitude of fourth texture data corresponding to terminal voltages received by the device are stored. A multitude of links linking each device instance to an associated device model, size parameters and instance parameters are stored. A quad having a size defined by the multitude of links is drawn by the quad in the GPU. Each thread in the quad is assigned to a different one of the multitude of links. The computations are carried out in each thread using the linked data to perform the model evaluation.

Model implementation on GPU

Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

Method and system for simulating dynamic behavior of a transistor

A solution of a first set of equations of the time-varying electrical response of a circuit is determined between pairs of adjacent time points tand tbased on predicted electrical responses of the devices at time point tand as a function of the initial temperatures of the circuit devices at time point t. A solution of a second set of equations of the time-varying temperature responses of devices of the circuit is determined (1) after each iteration of the first set of equations and as a function thereof or (2) at each time point tand as a function of the solution of the first set of equations at the time point to determine the corresponding temperature response of the circuit. The solutions of the first and second sets of equations at one or more of the points in time are displayed.

Circuit simulation with decoupled self-heating analysis

The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining whether entries in model stamping matrices interrelate according to a plurality of preset rules before circuit equations are solved.

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San Jose, CA, United States of America

Yutao Ma