Kabushiki Kaisha Toshiba

Fujitsu Corporation

Hitachi, Ltd.

Toshiba Electronic Devices & Storage Corporation

Fujitsu Semiconductor Limited

Hitachi Consumer Electronics Co., Ltd.

Toshiba Memory Corporation

Tokyo Shibaura Denki Kabushiki Kaisha

Sumitomo Heavy Industries, Ltd.

National Research Institute for Metals

The Nisshin Oil Mills, Ltd.

Fujisu Limited

National Research Institute

Yutaka Yamada

Tatsunori Kanai

Masaya Tarui

Hideki Yoshida

Satoru Murase

Teppei Tanaka

Kohei Miyoshi

Shigehiro Asano

Takashi Yoshikawa

Hidenao Kubota

Seiichi Sekiguchi

Yuzo Nishinaka

Mika Ri

Yoshiharu Yamashita

Noburu Fukushima

Kyoji Tachikawa

Hisashi Yoshino

Nobuyuki Isoshima

Toshihiko Matsuzawa

Yoshito Konno

Hiromi Niu

Shigeo Nakayama

Yasushi Naito

Yasuhiro Tomita

Masanori Takaji

Tatsuya Nakazawa

Satoshi Ishizuka

Misao Koizumi

Koji Suzuki

Junichi Kasai

Keiko Abe

Masataka Mizukoshi

Minoru Ikeda

Mitsuo Sasaki

Yasuo Yamagishi

Masahiro Yamamoto

Nobuo Kamehara

Takashi Yamamoto

Manabu Nishiyama

Michio Sono

Izumi Hirabayashi

Toru Sano

Yutaka Oki

Shuji Kato

Akira Takeda

Masayuki Ochiai

Katsunobu Kimura

Ichiro Yamaguchi

Ken Tanabe

Yohei Hasegawa

Koki Otake

Hiroaki Kumakura

Kazumasa Togano

Kazuhiko Mitobe

Takeshi Kodaka

Kazumi Matsumoto

Hidemi Yamada

Takanori Muramoto

Takemi Muroga

Machiko Shimizu

Yuichi Oda

Hidefumi Ueda

Susumu Abe

Ei Nakamura

Naofumi Takahashi

Yuki Iwane

Kazuo Watanabe

Toshihiro Tsutsui

Junji Sakuraba

Keisuke Adachi

Akihiko Kameyama

Kazuhiro Sunada

Ken Hattori

Katsushi Sakurane

Fumiaki Hata

Tsuginori Hasebe

Kazunori Jikihara

Chong C Kung

Hitoshi Wada

Toshiharu Niwa

Takeshi 406 Toshiba Oojima Apartment Araki

A motor controller includes a first control circuit, a second control circuit, a determination circuit, and a command circuit. The first control circuit outputs a first control value based on a rule base from a command value of an angular velocity and a measured value of an angular velocity. The second control circuit outputs a second control value based on a learned model from the command value of the angular velocity and the measured value of the angular velocity. The determination circuit determines a state based on at least the second control value. The command circuit acquires and outputs a control command value from the first control value and the second control value based on a result determined by the determination circuit.

Motor controller

According to one embodiment, a distance estimation device comprises a first distance estimation unit based on a first estimation method, and a second distance estimation unit based on a second estimation method different from the first estimation method. The second distance estimation unit is configured to change a part of the second estimation method according to an output of the first distance estimation unit.

Distance estimation device and distance estimation method

An image processing apparatus including a plurality of transfer units, a data storage, an image processing processor, and a test circuit. A plurality of captured image data are respectively assigned to the plurality of transfer units and the plurality of transfer units transfer the assigned image data. The data storage unit stores the plurality of image data which are transferred by the plurality of transfer units. The image processing processor performs image processing on the plurality of image data which are stored in the data storage unit. The test circuit tests the image processing processor in a period during which the image data are not input from the data storage unit to the image processing processor.

Image processing apparatus

According to one embodiment, a virtualization support device includes: a first processor controlling an operation of accelerators; a memory holding first information regarding a first application executed by a second processor, second information regarding a second application executed by the second processor, one or more first requests from the first application, and one or more second requests from the second application; and a management unit coupled to the first processor and the memory. The first processor performs arbitration of an order in which the accelerators execute the first and second requests, controls setting of the management unit by using the one of first and second information based on the arbitration, and causes the accelerators to execute one of the first and second requests based on the arbitration.

Virtualization support device, control method of virtualization support device, and calculation system

An arithmetic processing device according to an embodiment performs actual arithmetic processing for data inputted periodically and determination whether or not an error occurs in the actual arithmetic processing in real time. An ISP of this device includes an arithmetic processing circuit for performing image arithmetic processing for image data in moving image inputted from imaging device at each of frames, and a diagnostics control circuit and diagnostics processing circuit connected to the arithmetic processing circuit. The ISP, with these components, performs the image arithmetic processing for the image data in the moving image at each of the frames and error detection in the image arithmetic processing in real time.

Arithmetic processing device and method therefor

According to one embodiment, an image processing apparatus is provided with a first arithmetic unit, a second arithmetic unit, a third arithmetic unit, and a search unit. The first arithmetic unit calculates a first cost function. The first cost function represents a relation between a disparity value and a cost in a search range of a second image. The second arithmetic unit calculates a second cost function. The second cost function is a sum of first cost functions regarding a plurality of paths. The third arithmetic unit calculates a representative value of intermediate data. The intermediate data is an addition result of first cost functions regarding a first path group among the plurality of paths.

Image processing apparatus and image processing method

A virtual memory management apparatus of an embodiment is embedded in a computing machineand is provided with an application program, an operating system, a volatile memory, and a nonvolatile memory. The volatile memoryis provided with a plurality of clean pages. The nonvolatile memoryis provided with a plurality of dirty pages and a page table memory unit. The operating systemis provided with a virtual memory management unitwhich includes a page transfer unit

Device and memory system for storing and recovering page table data upon power loss

According to one embodiment, in a semiconductor device, a connection block includes multiple unit configurations, in each of which a first line extends along a first direction. A second line is placed above the first line and extends along a second direction which intersects with the first direction. A first variable resistance element has one end electrically connected to the first line and another end electrically connected to the second line. The third line is placed above the second line and extends along the first direction. A second variable resistance element has One end electrically connected to the second line and another end electrically connected to the third line. A fourth line is placed above the third line. The fourth line extends along the second direction. A third variable resistance element has one end electrically connected to the third line and another end electrically connected to the fourth line.

Semiconductor device

A memory system includes an encoding processing circuit configured to perform redundant encoding process on target data for generating data and a memory for writing the generated data by the encoding processing circuit, where a number of bits having a predetermined value are half or less than a total number of bits of the generated data.

Memory system having an encoding processing circuit for redundant encoding process

System and device for page replacement control between virtual and real memory spaces

In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.

According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

Memory device

A method of peeling an electronic component. The method includes a step of, when the electronic component is adhered onto a first main surface of a tape member, bringing a bellowphragm into contact with a second main surface, which is the other main surface of the tape member; and a step of, after the bellowphragm is brought into contact with the second main face, deforming the bellowphragm and the tape member by supplying a fluid to the bellowphragm to thereby peel the electronic component from the tape member.

Method and apparatus for peeling electronic component

Virtual memory management apparatus

Growing community of inventors

Kawasaki, Japan

Yutaka Yamada