Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Yutaka Tomisawa

Kazuhiko Inoue

Toshikazu Fukuda

Makoto Hideshima

Toru Suga

Bunshiro Yamaki

Keizo Tani

Tetsuo Ishii

Ken-ichi Muramoto

Sadatake Kikuchi

Tatsuro Mitani

A mold for molding a semiconductor package including a semiconductor chip mounted on a lead frame, wherein a major surface of the semiconductor chip is inclined relative to a surface of the semiconductor package, the mold includes a first mold half including a first mold cavity having a first mold surface and at least four first side surfaces, a second mold half including a second mold cavity having a second main surface extending substantially parallel to the first main surface and at least four second side surfaces extending substantially perpendicular to the second main surface, and a portion for supporting the lead frame and the semiconductor chip in the first and second mold cavities and position the major surface of the semiconductor chip in an inclined position relative to the second main surface, wherein the portion for supporting and positioning includes a first mating surface on the first mold half inclined relative to the first main surface and a second mating surface on the second mold half inclined relative to the second main surface.

Mold for molding a package for a semiconductor device for detecting or

A novel magnetoelectric element and a novel magnetoelectric apparatus convert a magnetic field into an electric capacitance and output it by utilizing the Lorentz force acting on a current in the magnetic field. The magnetoelectric element can convert a magnetic field into an electric capacitance and output it. The magnetoelectric apparatus includes the magnetoelectric element and an electric capacitance detecting unit, and can output a magnetic field as a change in frequency.

Magnetoelectric element and magnetoelectric apparatus

A semiconductor device for detecting or emitting a magnetic line of force or light is so provided that the major surface of its built-in semiconductor chip has a predetermined inclination angle relative to a mount surface of a mount substrate. An active layer of element for detecting a magnetic line of force or light or an element for emitting a magnetic line of force or light is formed on the major surface of the semiconductor chip. It is, therefore, possible to achieve a smaller mount thickness as defined relative to a mount surface and to detect a magnetic line of force or light coming in a direction parallel to the mount surface or to emit a magnetic line of force or light in a direction vertical to the mount surface.

Semiconductor device for detecting or emitting a magnetic line of force

A chip including a Hall element for detecting a magnetic force is p repared. On the chip is formed an unhardened magnetic resin layer, which is formed of a mixture of soft magnetic powder an dsilicone rubber. The unhardened magnetic resin layer is applied with a magnetic field and is stretched in a direction perpendicular to one face of the chip, so that its top portion is formed in a substantially conical shape and its bottom portion is formed in a substantially rectangular block, the ratio of the length Wa of its base to its height Wb, Wb/Wa, being equal to or greater than 1. The magnetic resin layer is then hardened. As a result, a magnetic force detecting semiconductor device is provided, which has a magnetic resin layer with a high magnetic force convergence that has its top portion formed in a conical shape and its bottom portion formed in a rectangular block, the ratio of the length of its base to its height being equal to and greater than 1.

Magnetic force detecting semiconductor device and method for

A GaAs planar diode includes an N type GaAs substrate having an N.sup.+ GaAs layer on which an N.sup.- GaAs layer is formed. A first impurity layer of the N.sup.+ type is formed on the N.sup.31 GaAs layer. A second impurity layer of a p.sup.+ type is formed on the first impurity layer, wherein a p-n junction is formed between the first and second impurity layers. A semi-insulation region, for encompassing a predetermined area of the p-n junction of the first and second impurity layers, is formed in the substrate. The depth of the semi-insulation region in the substrate is deeper than the total depth of the first and second impurity layers, so that the semi-insulation region serves as an element isolation region of the p-n junction of the first and second impurity layers.

GaAs plannar diode and manufacturing method therefor

Disclosed is a semiconductor device having a field effect transistor (FET) formed in a semi-insulative substrate. A positive bias voltage equal to or higher than the bias voltage applied to the drain electrode of the FET is applied to a back surface electrode formed on the back surface of the substrate, with the result that the electrons generated within the semi-insulative substrate are pulled into the back surface electrode so as to prevent said electrons from flowing into the drain region and, thus, to prevent the drain current vibration.

Semiconductor device formed in semi-insulative substrate

A semiconductor pressure sensor wherein a semiconductor chip of diaphragm type is supported by a mount plate through a thin tubular supporting member or a pressure inlet tube having a coefficient of thermal expansion similar to that of a substrate constituting the semiconductor chip. The semiconductor chip is fixed to the thin tubular supporting member or the pressure inlet tube by means of a bonding material, and the thin tubular supporting member or the pressure inlet tube is fixed by means of a bonding material having a high bonding strength with respect thereto, thus absorbing thermal stress produced due to the difference in coefficient of thermal expansion.

Semiconductor pressure sensor

A junction type semiconductor device, wherein a protective diode is formed in a part of the region consisting of a base region and a collector region. The device permits reducing the manufacturing cost of semiconductor elements, makes it possible to provide a smaller electric apparatus, and is high in reliability.

Semiconductor device

A junction type field effect transistor comprising a semiconductor substrate; semiconductor regions formed in the semiconductor substrate and exposed on a major surface thereof, the semiconductor regions including a gate region and an isolation region; and a polycrystalline semiconductor layer formed on the surface of the gate region or on the surfaces of the gate region and the isolation region. The polycrystalline semiconductor layer contains an impurity of the same conductivity type as the gate and the isolation regions.

Growing community of inventors

Yokohama, Japan

Yutaka Tomisawa