Hitachi-High-Technologies Corporation

Yutaka Tandai

Tamao Ishikawa

Takehiro Hirai

Katsuhiko Ichinose

Tsunehiro Sakai

Shigeki Kurihara

Yuji Takagi

Takashi Noguchi

Hideyuki Kazumi

Akira Ikegami

Yuichi Hamamura

Seiji Isogai

Yohei Minekawa

Tomohiro Funakoshi

Hideto Dohi

Shigetoshi Sameshima

Kazuhisa Hasumi

Yuta Kawamoto

Manabu Yano

Koichi Hayakawa

Kazunori Nemoto

A purpose of the present invention is to provide a charged particle beam device that suppresses an off-axis amount when a field of view moves, said move causing an aberration, and allows large field of view moves to be carried out. In order to achieve the above-mentioned purpose, this charged particle beam device is provided with an objective lens and deflectors for field of view moves, said deflectors deflecting a charged particle beam, and is further provided with an accelerating tube positioned between the objective lens and the deflectors for field of view moves, a power source that applies a voltage to the accelerating tube, and a control device that controls the voltage to be applied to the power source in response to the deflection conditions of the deflectors for field of view moves.

Charged particle beam device

A defect image classification apparatus includes a control unit that selects images obtained from at least some detectors among a plurality of detectors, associated with kinds of defects to be a classification result of an automatic defect classification processing unit, as images displayed initially on a display unit. The control unit associates the kinds of the defects and the images displayed initially on the display unit, on the basis of a switching operation log when a user classifies images of defects determined previously as the same kinds as the kinds of the defects determined by the automatic defect classification processing unit.

Defect image classification apparatus

The present invention provides semiconductor defect classification equipment for classifying a defect in a semiconductor wafer. The semiconductor defect classification equipment is provided with: a display unit; a storage unit that stores an inspection image including an inspection object portion on the semiconductor wafer and design data of the semiconductor wafer including a plurality of manufacturing steps; and an processing unit that displays the inspection image and the design data on the display unit. The processing unit acquires at least one first layout data and the inspection image from the storage unit, and displays the first layout data and the inspection image on the display unit in a superposed manner.

Semiconductor defect categorization device and program for semiconductor defect categorization device

A defect image processing apparatus uses a normalized cross correlation to image-match a layout image () acquired from a design data with an image acquired by removing, from a defect image (), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image () on the display device. In the displayed layout image & defect image (), not only the layout image, the layer of which is the same as that of the defect image (), but also a layout image of another layer is displayed superimposed on the defect image (). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

Defect image processing apparatus, defect image processing method, semiconductor defect classifying apparatus, and semiconductor defect classifying method

A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.

Semiconductor defect classifying method, semiconductor defect classifying apparatus, and semiconductor defect classifying program

There is provided an evaluation object pattern determining apparatus capable of determining local patterns to be evaluated. The apparatus is for use in a pattern evaluating system storing patterns of a LSI chip as CAD data, picking out coordinates of local patterns whose process margin is small from the CAD data by way of simulation and assisting observation of the local patterns produced in a fabrication line. The apparatus includes a risk level map creating section for creating risk level maps in which risk areas are disposed. The risk area is assigned with a risk level obtained by digitizing that the risk area is an area whose process margin is smaller than other areas. The apparatus also includes a superimposition processing section for superimposing the coordinates of the local patterns with the risk level map to pick out the coordinates of the local patterns located within the risk area.

Evaluation object pattern determining apparatus, evaluation object pattern determining method, evaluation object pattern determining program and pattern evaluating system

Growing community of inventors

Tokyo, Japan

Yutaka Tandai