Fujitsu Corporation

Fujitsu Microelectronics Limited

Fujitsu Microcomputer Systems Limited

Yutaka Takinomi

Hiroyuki Abe

Jun Yoshida

Minoru Wano

Kazushi Sawai

Shinichi Watanabe

A relay board provided in a semiconductor package where a plurality of semiconductor chips are provided, the relay board relaying a wire for wiring the semiconductor chips or a wire for wiring a lead frame of the semiconductor package and the semiconductor chip, the relay board includes a plurality of wirings each of the wirings connecting at least three bonding pads.

Relay board with bonding pads connected by wirings

A semiconductor device capable of effectively eliminating noise on multilayered power lines with a bypass capacitor. A first power line is connected to the bypass capacitor. A second power line is a line from which a part located above the bypass capacitor is removed. Contacts connect the first and second power lines. Therefore, noise appearing on the second power line travels to the first power line, resulting in effectively eliminating the noise with the bypass capacitor.

Semiconductor device

In a semiconductor chip, a second power source pad, to which a ground potential is applied, is arranged adjacent to a first power source pad, to which a power source potential is applied, signal pads are arranged adjacent to the second power source pad by the number corresponding to a size of an external part such as a bypass capacitor inserted between power source terminals in an IC chip, and further, a third power source pad, to which the ground potential is applied, is arranged adjacent to the signal pad. The second power source pad or the third power source pad is selected according to the size of the external part, and then, is connected to a lead terminal, to which the ground potential is applied, in an IC chip, thereby providing a power source terminal, to which the ground potential is applied.

IC chip

A level converter includes a first circuit which converts a first level of a signal into a second level which is higher than the first level, and a second circuit which causes a potential of a given node of the level converter to be defined rapidly when the level converter is in a state other than a normal state in which the first circuit converts the first level of the signal into the second level.

Level converter and semiconductor device

A pattern display signal generating apparatus comprises a memory for storing predetermined pattern data and for outputting even-numbered bits and odd-numbered bits of the pattern data in parallel when scanned, a timing generator for generating an address for scanning the memory and for generating first and second clock signal having a predetermined phase difference, a first shift register for shifting the odd-numbered bits and outputting the same in series in synchronization with the first clock signal, a second shift register for shifting the even-numbered bits and outputting the same in series in synchronization with the second clock signal, and a logical operation circuit for performing at least one predetermined logical operation between outputs of the first and second shift registers to generate a pattern display signal.

Growing community of inventors

Kawasaki, Japan

Yutaka Takinomi