Apple Inc.

Yutaka Takahashi

Sushma Shrikant Trivedi

Joseph P Bratt

Vaughn Todd Arnold

Jack Benkual

Mushtaq A Sarwar

Derek Fujio Iwamoto

Alexei V Ouzilevski

Steven Todd Weybrew

David Ligon

At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.

Memory controller chipset

Methods and apparatuses for decoding a compressed video stream. In one aspect of the invention, a method to decode a variable length encoded bit stream includes: concurrently processing first data obtained from variable length decoding a first code word in a register while variable length decoding a second code word in the register. In one example, processing the first data includes: looking up an inverse zigzag index; computing an Inverse Direct Cosine Transformation (IDCT) coefficient; storing the IDCT coefficient in a buffer in a transposed inverse zigzag order; and branching conditionally based on a condition encountered in variable length decoding the first code word.

Method and apparatus for variable length decoding and encoding of video streams

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Cupertino, CA, United States of America

Yutaka Takahashi