Kabushiki Kaisha Toshiba

Yutaka Shirai

Hiroyuki Koinuma

Toshiki Hisada

A counter circuit, which may be on a semiconductor integrated circuit, that is applicable to both a linear sequence and an interleave sequence and is capable of setting a burst length at 1, 2, 4, 8, or 2.sup.n in both sequences. The burst length of the counter circuit may be changeable, and the counter circuit may output a signal indicating whether the count number has reached the burst length.

Counter circuit and semiconductor memory having counter circuit as

An internal power supply voltage generation circuit used for a semiconductor memory device is disclosed. The semiconductor integrated circuit device includes a memory unit for storing data, and an internal power supply voltage generation unit for generating an internal power supply voltage VINT from an external power supply voltage VCC. The internal power supply voltage generation unit has a standby internal power supply voltage generation circuit and an activation internal power supply voltage generation circuit. The activation internal power supply voltage generation circuit is controlled by a control circuit. When a plurality of banks are set in the memory unit, the control circuit activates the activation internal power supply voltage generation circuit while at least one bank is active.

Semiconductor memory device including an internal power supply circuit

The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.

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Yokohama, Japan

Yutaka Shirai