Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Ricoh Company, Ltd.

Yutaka Shimizu

Ichiro Seto

Shoji Ootaka

Katsuya Nonin

Hiroyuki Kobayashi

Masaru Koyanagi

Satoshi Inoue

Takayuki Kato

Masaki Nishikawa

Mikihiko Ito

Yasuhiro Hirashima

Kei Shiraishi

Ryuichi Fujimoto

Rui Ito

Yuji Satoh

Shigeyasu Iwata

Fumiya Watanabe

Yoshiharu Nito

Makoto Morimoto

Yumi Takada

Isao Fujisawa

A distance measuring device includes a calculating section that calculates, based on phase information acquired by a first device and a second device, at least one of which is movable, a distance between the first device and the second device. The first device includes a first transceiver that transmits three or more first carrier signals and receives three or more second carrier signals using an output of a first reference signal source. The second device includes a second transceiver that transmits the three or more second carrier signals and receives the three or more first carrier signals using an output of a second reference signal source. The calculating section calculates the distance based on a phase detection result obtained by reception of the first and second carrier signals and corrects the calculated distance based on information concerning an amplitude ratio of the first carrier signals received by the second transceiver.

Distance measuring device and distance measuring method

There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.

Semiconductor integrated circuit and semiconductor storage device

In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.

Semiconductor memory device and method for adjusting threthold voltage thereof

A distance measuring device includes a calculating section configured to calculate, based on phase information acquired by a first device and a second device, at least one of which is movable, a distance between the first device and the second device. The first device includes a first reference signal source and a first transceiver configured to transmit two or more first carrier signals and receives two or more second carrier signals using an output of the first reference signal source. The second device includes a second reference signal source configured to operate independently from the first reference signal source and a second transceiver configured to transmit the second carrier signals and receives the first carrier signals using an output of the second reference signal source. The calculating section calculates the distance based on a phase detection result obtained by reception of the first and second carrier signals.

A semiconductor integrated circuit includes a pair of differential signal lines including first and second signal lines, a first comparator, and a second comparator. The first comparator is configured to output at least one of a first signal corresponding to a difference between a potential of a first input node and a potential of a second input node, and a second signal corresponding to a difference between a potential of a third input node and a potential of a fourth input node. The second comparator is configured to output at least one of a third signal corresponding to a difference between a potential of a fifth input node and a potential of a seventh input node, and a fourth signal corresponding to a difference between a potential of a sixth input node and a potential of a eighth input node.

Semiconductor integrated circuit, receiving device, and communication system

A clock and data recovery device includes an extraction circuit and a phase detection circuit. The extraction circuit extracts transition information including data information corresponding to a value of data and edge information corresponding to transition of the value of the data, from a multivalued input data signal subjected to pulse amplitude modulation in synchronization with a clock from an oscillator. The phase detection circuit uses transition information selected based on a predetermined condition, when executing a phase error determination of the clock with respect to the input data signal based on the transition information extracted by the extraction circuit.

Clock and data recovery device and phase detection method

A transmission apparatus includes a waveform processing circuit. The waveform processing circuit is configured to receive a modulated signal indicating each of values of pulses by one of four signal levels including first, second, third, and fourth signal levels ascending in this order. The waveform processing circuit is configured to output a signal corresponding to the modulated signal. A portion of the output signal corresponding to a portion of the modulated signal that transitions between the first and fourth signal levels, transitions between a first adjusted signal level different from the first signal level and a second adjusted signal level different from the fourth signal level. The transmission apparatus is configured to transmit a signal corresponding to the signal output from the waveform processing circuit through a wired communication path.

Transmission apparatus and communication system

According to one embodiment, a transmitter includes a first buffer, a second buffer, a logic circuit, and a class E power amplifier. The first buffer receives a first sinusoidal signal, and converts the first sinusoidal signal to a first rectangular wave signal. The second buffer receives a second sinusoidal signal having a phase delay with respect to the first sinusoidal signal, and converts the second sinusoidal signal to a second rectangular wave signal. The logic circuit receives the first and second rectangular wave signals, and performs logical operation processing on the first and second rectangular wave signals to generate a logic signal with a predetermined duty cycle. The class E power amplifier receives the logic signal, and performs amplification operation based on the logic signal.

Transmitter with class E amplifier

A voltage controlled oscillator has an amplifier circuit which includes an inductor and a variable capacitance element, and outputs an oscillation signal of an oscillation frequency corresponding to an oscillation frequency control voltage supplied to the variable capacitance element; and a power supply circuit which supplies an operation current to the amplifier circuit, wherein by changing the operation current outputted from the power supply circuit in a state where the oscillation frequency control voltage is fixed to a desired value, a value of the operation current at which the oscillation frequency of the oscillation signal takes a value in the vicinity of a maximum value, is extracted, and the extracted value of the operation current is set as a value of the operation current outputted from the power supply circuit.

Voltage controlled oscillator with operation current adjusting device

An amplifier circuit is provided with a control section that respectively selectively supplies either a second voltage or a third voltage to gates of a plurality of second transistors and gates of a plurality of third transistors by respectively switching the connection states of a plurality of first switching elements and a plurality of second switching elements to their first input terminal sides or to their second input terminal sides.

Amplifier circuit and gain control method thereof

A portable information processing apparatus includes a memory, an AC/DC converter, a built-in battery, a power source detection mechanism, and a switch. The memory includes a main memory block and a sub memory block. The AC/DC converter converts an AC voltage to a DC voltage supplied to the memory. The built-in battery supplies a battery DC voltage supplied to the memory. The power source detection mechanism detects whether the apparatus operates with the converted AC to DC voltage or the battery DC voltage. The power source detection mechanism generates a detection signal when detecting the battery DC voltage. If the switch receives no detection signal from the power source detection mechanism, the switch supplies the converted AC to DC voltage and the battery DC voltage to the main and sub memory blocks. Otherwise, he switch shuts off a supply of the battery DC voltage to the sub memory block of the memory when receiving the detection signal from the power source detection mechanism.

Power saving for a portable information processing apparatus using switch that shuts off power to sub memory block when in battery mode and supplies power when in AC mode

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Yokohama Kanagawa, Japan

Yutaka Shimizu