Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Yutaka Shimbo

Katsuyuki Sato

Takeshi Kajimoto

Michitaro Kanamitsu

Nobuo Kato

Masahiro Ogata

Kanehide Kenmizaki

Kiichi Manita

Shouji Kubono

Mitsuteru Kobayashi

The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal. Such availability of plural self-refresh modes becomes particularly advantageous when considering consumption of the back-up power for maintaining the IC memory device versus stability of stored data. While the consumption of the back-up power for maintaining the device would be relatively lower under one of the self-refresh modes, namely, the PS (pseudo) refresh mode, the stability of data stored would, however, be greater under another self-refresh mode, namely, the VS (virtual) refresh mode.

Semiconductor memory device facilitated with plural self-refresh modes

In LSI circuit devices having a plurality of subchips packaged therein and having specific functions, capacitance cutting buffer circuits are employed in conjunction with respective terminals of the subchips, and a driver is disposed at respective points where relatively long wiring lines are respectively sub-divided into a corresponding plurality of lines. As a result, signal transmission delay can be significantly reduced. The terminals of the subchips are also provided with a probing pad to test the operations of the subchips independently of one another. The subchips employ circuit blocks which are to operate simultaneously and in conjunction with the wirings of the subchips, power supply lines are disposed correspondingly to the distributively arranged circuit blocks. Bus lines also controllably transmit addresses as well as data signals in a time sharing manner. Furthermore, each of the subchips has a fault test circuit. The subchips which have a DC fault is electrically isolated thereby allowing the remainder of the subchip to be usable. In the fault relieving technique employed, a combination of memory locations wherein no fault exists is selected for use, thereby allowing the construction of an LSI even with subchips which correspond to faulty bit addresses. The fault relieving technique employed uses an address converting circuit for faulty addresses, this operation being performed automatically within the chip system.

Large-scale semiconductor integrated circuit device and method for

There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.

Semiconductor memory, components and layout arrangements thereof, and

A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.

Data output buffer for a semiconductor memory

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Hino, Japan

Yutaka Shimbo