Synaptics Corporation

Renesas Electronics Corporation

Synaptics Japan Gk

Nec Electronics Corporation

Yutaka Saeki

Kiyoshi Miyazaki

Teru Yoneyama

Yoshinori Ura

Isao Henmi

Taisuke Koshino

Kenichi Kaneshige

Akihiro Hiramatsu

A mixed signal circuit includes a logic circuit, an analog circuit, a logic supply line, a first regulator circuit, and a second regulator circuit. The analog circuit is configured to receive an analog supply voltage. The logic supply line is coupled to the logic circuit. The first regulator circuit includes an output p-channel metal oxide semiconductor (PMOS) transistor having a drain coupled to the logic supply line and a first former stage configured to receive a first logic supply voltage to drive a gate of the output PMOS transistor. The second regulator circuit includes an output n-channel metal oxide semiconductor (NMOS) transistor having a source coupled to the logic supply line and a second former stage configured to receive the analog supply voltage to drive a gate of the output NMOS transistor. The analog supply voltage is higher than the first logic supply voltage.

Device and method for supplying logic supply voltage in mixed signal circuit

A current source circuit includes a plurality of current generation subcircuits and an operational amplifier. Each of the plurality of current generation subcircuits includes an output transistor having a drain through which an output constant current is generated, a resistor coupled between a first constant voltage node and a source of the output transistor, and a storage capacitor coupled between the first constant voltage node and a gate of the output transistor. The operational amplifier has a first input coupled to a second constant voltage node, a second input selectively couplable to the source of the output transistor, and an output selectively couplable to the gate of the output transistor.

Current source circuits tolerant of transistor characteristics variations

Regulator circuitry includes first to third output transistors, a first control transistor and a circuit stage. The first and second output transistors, and the first control transistor have a first channel conductivity type. The second output transistor has a second channel conductivity type. The first and second output transistors have a drain coupled to an output node and a source coupled to a first power supply line. The third output transistor has a drain coupled to the output node and a source coupled to a second power supply line. The circuit stage is configured to drive the gates of the first output transistor, the third output transistor, and the first control transistor based on a specified level of the output voltage.

Low power consumption regulator circuitry

An operational amplifier includes an output transistor having a gate coupled to an output node, at least one intermediate transistor each having a common gate node, an input transistor having a gate coupled to an input node, and a load device coupled to sources of the output transistor, the at least one intermediate transistor, and the input transistor. The operational amplifier further includes an output stage coupled to the output node, configured to drive the voltage on the output node based on currents through the output transistor, the at least one intermediate transistors, and the input transistor. The operational amplifier further includes a first switch coupled between the common gate node of the at least one intermediate transistor and the gate of the input transistor, and a second switch coupled between the output node and the common gate node of the at least one intermediate transistors.

Operational amplifier with reduced input capacitance

An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.

Operational amplifier, integrated circuit, and method for operating the same

A display driver comprises: a first grayscale line; output circuitry configured to receive a first grayscale voltage from the first grayscale line and perform digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the first grayscale voltage; and first gamma assist circuitry comprising a first holding node to hold the first grayscale voltage received from the first grayscale line and configured to drive the first grayscale line based on a first voltage between the first holding node and the first grayscale line.

Method and system for stabilizing a source output voltage for a display panel

An operational amplifier includes a first transistor, a second transistor, a third transistor, a first constant current source, an output state, a first switch, and a second switch. The first transistor has a first gate configured to receive an output voltage from an output node. The second transistor has a second gate. The third transistor has a third gate configured to receive an input voltage. The first constant current source is coupled to sources of the first transistor, the second transistor, and the third transistor. The output stage is configured to drive the output voltage on the output node based on a first current through the first transistor, a second current through the second transistor, and a third current through the third transistor. The first switch is coupled between the second gate of the second transistor and the third gate of the third transistor; and the second switch is coupled between the output node and the second gate of the second transistor.

A display driver comprises a digital-to-analog converter (DAC) configured to output a grayscale voltage corresponding to an image data. The display driver further comprises a source amplifier configured to drive a source line of a display panel, and a buffer connected between the DAC and the source amplifier. The buffer comprises a first NMOS transistor having a gate supplied with the grayscale voltage and a drain connected to a power supply. The buffer is configured to supply a current depending on a first current flowing through the first NMOS transistor to an input terminal of the source amplifier.

Device and method for driving display panel

The overdrive amplifier may include: a differential input circuit arranged by connecting, in a folded-cascode style, input transistors supplied with an input signal at gates, and feedback input transistors accepting the feedback of an output signal at respective gates; a current mirror load having mirror input current paths connected to current paths of the feedback input transistors, and mirror output current paths connected to current paths of the input transistors; an output circuit accepting the input of output control signals from the mirror output current paths of the current mirror load; and an overdrive circuit which causes bias currents of directions which boost an output of the output circuit, depending on the output control signals, to pass through the current mirror load based on the output control signals in an overdrive period.

Overdrive amplifier and semiconductor device

The booster precharges a boost-voltage-output terminal to a predetermined voltage before voltage-boosting start by a charge-pump circuit in the booster. While alternately switching one capacitive electrode of a pumping capacitance between first and second voltages, the charge-pump circuit periodically applies a third voltage to the other capacitive electrode, in which the voltage is boosted by lifting up the third voltage each switching. The resultant boost voltage is successively supplied to a stabilization capacitance through a MOS switch circuit for output. Thus, a boost voltage boosted to a sum voltage of the second and third voltages can be obtained. Using a precharge voltage produced by the precharge circuit in the booster as the third voltage can make a MOS switch circuit operable to supply the third voltage and the MOS switch circuit for boost voltage output smaller than a voltage under the sum voltage of the second and third voltages.

Semiconductor device with booster part, and booster

An integrated circuit device boosts an output voltage which is to be boosted based on the reference power supply voltage, based on another power supply voltage before the reference power supply voltage is supplied.

Device and method for voltage boosting and display panel driver incorporating the same

A differential amplifier circuit and display drive circuit having the same are disclosed herein. In one example, a differential amplifier circuit includes a differential pair transistor configure to receive a differential input signal. A current source is connected in series to the differential pair transistor and an output transistor that drives an output terminal on the basis of the differential input signal. The output transistor is configured to increase a current value of a current source on the basis of a timing at which a voltage level of the output terminal is caused to transition. The output transistor is configured to drive the output terminal only during a period in which the output terminal is caused to transition, and thus a slew rate is improved by increasing a bias current of the differential pair transistor in the period.

Differential amplifier circuit and display drive circuit

In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage.

Level shift circuit and drive circuit of display device

A current driving circuit includes a constant current source circuit delivering a driving current to a load, and an output voltage difference amplifier circuit detecting a voltage change produced at a load driving end during a preset time period and delivering a current or a voltage corresponding to the voltage change to the load during a time period different from the preset time period. During first time period, capacitance circuit compares potential during a preceding time period to that during the current time period, and causes a potential at the load driving end during the current time period to store in any of capacitance elements depending on result of comparison. The amplifier circuit buffering an average value of the potential values stored in the capacitance elements during the second time period following the first time period, to deliver the average value to the load.

Current driving circuit

A signal transfer circuit according to the present invention includes a differential signal generation unit that generates a differential signal according to a voltage difference between two input signals, a voltage difference detection unit that detects a voltage difference between the two input signals input to the differential signal generation unit, and a signal output unit that outputs a signal including a predetermined value if the voltage difference is not detected by the voltage difference detection unit, and outputs the differential signal generated by the differential signal generation unit if the voltage difference is detected by the voltage detection unit.

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Kanagawa, Japan

Yutaka Saeki