Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electrical Industrial Co., Ltd.

Yutaka Nio

Naoji Okumura

Yosuke Izawa

Toshiro Nishio

Masahiro Tani

Katsumi Terai

Hidekazu Suzuki

Kazuto Tanaka

Toshiaki Kitahara

Toshichika Sato

Kazuhito Tanaka

Masazumi Yamada

Satoshi Okamoto

Takashi Yamaguchi

Hideyo Uwabata

Atsushi Ishizu

Ryuji Matsuura

Chikara Gotanda

Kouichiro Nagata

Koichi Tanaka

Kazuya Ueda

Kiyoshi Imai

Yutaka Nishikawa

Taro Funamoto

Hiroki Monta

Yoshihito Ohta

Toyoaki Unemura

Ken Sakamoto

Hideto Nakahigashi

Minoru Miyata

Masaaki Fujita

Satoru Inagaki

Tetsuji Maeda

Kenjirou Tsuda

Etsuyoshi Sakaguchi

Koichiro Nagata

Shuuhei Taniguchi

Takao Hasegawa

Shingo Miyauchi

Naoki Kurita

Tomoko Morita

Keiya Miyoshi

Mitsuji Okawa

Matsuura Ryuji

Maoji Okumura

Toshiohika Sato

Miho Nagai

Masazumi c/o Matsushita Electric Industrial Co Ltd Yamada

An image display device includes: an interpolation phase generator that generates an interpolation phase on the basis of downsampling frame information representing a downsampling timing at which at least one frame image of the image signal is thinned, and an interpolation frame generator that generates an interpolation frame image corresponding to the interpolation phase. The interpolation phase generator generates the interpolation phase such that a phase distance between a first interpolation frame image from among a plurality of interpolation frame images within one period of downsampling periods, and a second interpolation frame image that follows the first interpolation frame image becomes equal to a phase distance between mutually adjacent interpolation frame images obtained when phase distances between a plurality of interpolation frame images are equalized within one period of the downsampling periods.

Image display device and image processing device

In a transmission device: a controller performs a control of reading, from information regarding video specification, first information indicating whether a reception device is capable of intermittent reception of receiving a video signal at a timing that causes certain number of frames to be intermittent, and, when the reception device can perform intermittent reception, multiplexing, to the video signal during a blanking period of the video signal to be updated, an enable signal indicating the present video signal is to be enabled and second information indicating that transmission of the video signal will not resume unless the video signal is updated; and a transmitter transmits the video signal that is to be updated and then does not resume transmission of the video signal unless the video signal is updated.

Baseband video data transmission device and reception device, and transceiver system with reduced power consumption by intermittent transmission reception of a video signal

In a transmission device: a controller performs a control of reading, from information regarding video specification, information regarding a horizontal resolution and a vertical resolution that are supported by a reception device and information regarding frame rate that is supported by the reception device, and multiplexing, to the video signal during a blanking period of the video signal, information indicating a reduce frame rate that is selectable from a range supported by the reception device; and a transmitter transmits baseband video data at the reduced frame rate.

Transmission device and reception device for baseband video data, and transmission/reception system

The present invention provides an image processing device that converts an interlace image signal into a progressive signal so as not to cause degradation of image quality in edge parts of letters or the like, when performing an IP conversion with respect to an image that is mixed with an OSD such as a caption and a telop. The image processing device includes: an OSD mix part that mixes an on-screen display with an input interlace image signal; a motion detecting part that detects a motion by comparing pixel data between different fields; and an interpolation pixel generating part that generates a new pixel between lines of the interlace image signal by interpolating calculation with an interpolation method that depends on an OSD mix ratio of the OSD mix part and a result of the motion detection by the motion detecting part.

Image processing device

An audio controlling device generates an audio mute signal based on the level of a power-supply voltage supplied from the source equipment, whether a clock signal has been input or not, whether a digital signal has been input or not, whether a multiplier circuit is being locked or not, an error rate, whether an audio clock detection circuit is being locked or not, the presence or absence of a change in a control signal, and whether a synchronization detection circuit is stable or not. The audio controlling device applies the audio mute signal to an audio mute circuit, while applying an OSD control signal to an OSD processing circuit. The audio mute circuit is placed in a mute state or unmute state based on the audio mute signal. The OSD processing circuit provides the on-screen display of a message based on the OSD control signal.

Digital interface receiver apparatus

When the HPD () which indicated that the transmission of a control signal between the data receiving apparatus () and the control signal receiving apparatus () has become possible is detected, the command judging section () ignores the first reception command which it directly received from the remote controller () and makes the second reception command () effective which it receives via the CEC line (). In such a construction, it is possible to conduct a remote control operation normally without affecting unfavorable influences on the apparatuses.

Control signal receiving apparatus

A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.

Digital interface decode receiver apparatus

A signal transmission system: that includes a signal transmission unit () that includes a MPEG decoder (), which receives digital broadcasting and outputs a luminance signal Y and two color difference signals P/P, and a transmission path encoding circuit (), which encodes the YPPoutputted from the MPEG decoder () into signals in the forms suited to a transmission path and transmits the encoded signals; and a signal reception unit () that includes a transmission path decoding circuit (), which receives the encoded YPPand decodes them, a Y processing circuit (), which processes the decoded luminance signal Y, a chrominance processing circuit (), which processes the respective decoded color difference signals P/P, a signal conversion circuit (), which converts the YPPoutputted from the Y processing circuit () and the chrominance processing circuit () into RGB signals, and a display device () which displays the RGB signals.

Signal transmission system

On a display () end, maker codes and device codes are read from all STBs () connected to the display () to create a connected-device table. When a user presses a button on a remote controller, the display receives a remote control code outputted from the remote controller, searches the connected-device table for a maker code and a device code that match the maker code and the device code included in the remote control code, controls a selector () so that a reception interface that is connected to an STB whose maker code and device code match those included in the remote control code is connected to a display section (), thereby to display AV data transmitted from the STB on the display section ().

Audio visual system

A signal transmitter and a signal receiver comprises a time base compression part () for compressing an audio signal on a time base to output the compressed signal as a time base compressed audio signal and a multiplexing part () for multiplexing a video signal, a control signal, and the time base compressed audio signal to output the multiplexed signal to the external as a video/audio control multiplexed signal. The thus constituted signal transmitter and the signal receiver realize a signal transmission system for multiplexing and transmitting the video signal, audio signal, and control signal, for consequently transmitting high-quality diverse digital audio signals without conversion into an analog signal, and for transmission at high speed with minimal error.

Signal transmitter and signal receiver

In a baseband video transmission system for transmission of a video signal at a baseband based on the DVI standard, a transmitting device multiplexes a data signal representing data other than video during at least one blanking period of component video signals of the video signal to generate a DVI signal. A receiving device receives the DVI signal, and extracts the data signal from the received DVI signal.

Baseband video transmission system

A ringing detector detects mosquito noise and ringing for outputting an image signal smoothed by a horizontal/vertical high-pass filter when mosquito noise and ringing are detected while outputting the image signal as such when neither mosquito noise nor ringing is detected, thereby properly correcting the image signal without reducing the texture specific to the image signal also in a portion continuously exhibiting fine details.

Noise detector, noise detection method, signal processor and signal processing method

A vertical HPF and a horizontal HPF receive a video signal , and extract only a high frequency component in the vertical/horizontal directions, respectively. Absolute value taking parts take an absolute value of the high frequency components, respectively, and change their values to positive values. A horizontal accumulating/adding part and a vertical accumulating/adding part accumulate/add an input signal so as to output a vertical one-dimensional signal and a horizontal one-dimensional signal, respectively, each periodically having a peak value in the respective vertical and horizontal directions. A horizontal peak detecting part detects a horizontal peak position according to the horizontal one-dimensional signal. A vertical peak detecting part detects a vertical peak position according to the vertical one-dimensional signal and identifies a format thereof. A binarization part obtains a block boundary image, according to the horizontal peak position and the vertical peak position, in which pixel positions having a peak are provided with 1 and remaining pixel positions are provided with 0. In this manner, even if a block boundary to eliminate block noise thereon is not clearly identified, it becomes possible to correctly detect and eliminate the block boundary.

Block noise detector and block noise eliminator

A video signal processing circuit synthesizes a video signal and a graphic signal on the basis of a display switching control signal, inverts a synthesized signal on the time axis for each of a forward scanning period and a backward scanning period, and output a display signal. A speed modulating signal control circuit inverts the binarized display switching control signal on the time axis for each of the forward scanning period and the backward scanning period, expands the pulse width thereof, and feeds the display switching control signal to a speed modulating signal generating circuit. The speed modulating signal generating circuit subjects a display signal to first-order differentiation, inverts the polarity of a differentiated signal in the backward scanning signal, sets a portion, corresponding to the graphic signal, in the differentiated signal on the basis of the display switching control signal at a zero level, and generates a speed modulating signal.

Image display and horizontal speed modulator

A video signal processing apparatus which can process video signals with different formats simply by switching between programs for processing video signals. Different system clock signals are sent to the input and output processes by employing a programmable signal processor , input synchronizing signal processor , programmable signal processor and output synchronizing pulse processor . A method for processing the video signal can be flexibly changed simply by switching between signal processing programs for programmable signal processors. In addition, the use of a memory enables the signal, which is processed using the system clock signal in the input process, to be processed using the system clock signal in the output process. The present invention thus allows the processing of video signals with many different signal formats. The design of efficient circuitry will greatly reduce costs and production processes.

Video signal processing apparatus

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Osaka, Japan

Yutaka Nio