International Business Machines Corporation

Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Kabushiki Kaisha Toshiba

Sandisk Corporation

Magic Technologies, Inc.

Matsushita Electric Works, Ltd.

Samsung Electronics Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Rohm Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Yutaka Nakamura

Robert K Montoye

Hiroyuki Yamada

Leland Chang

Hem P Takiar

Robert C Miller

Hiroyuki Shigematsu

Hiroyuki Sakamoto

John Kenneth DeBrosse

Masatoshi Ishii

Takeo Yasuda

Kohji Hosokawa

Junka Okazawa

John Debrosse

Hiroshi Nakao

Hsu-Kai Yang

Masayuki Kozuka

Makoto Tatebayashi

Hirohisa Tanaka

Shunji Harada

Hiroyuki Nagasawa

Masaaki Kurata

Munenori Sakamoto

Yasuhiro Nakajima

Jun Sawada

Tomoaki Izumi

Chen Guo

Hiroshi Nishida

Masamitsu Takahashi

Manabu Inoue

Todd Edward Takken

Jeffrey Haskell Derby

Yoshihisa Kato

Masahiro Nakanishi

Takashi Suzuki

Toshio Sunaga

Norihito Tsukahara

Xin Zhang

Masayuki Toyama

Hsu Kai Yang

Tetsushi Kasahara

Kenji Nishimura

Daido Komyoji

Hidenobu Nishikawa

Hiroshi Suenaga

Kazuaki Tamura

Kiminori Matsuno

Junji Tanaka

Shozo Ochi

Aki Miake

Yoshiteru Mori

Yukihiro Fukumoto

Hideki Kawai

Shuichi Takeda

Martin Cochet

Tadashi Satake

Hiroshi Okuno

Makoto Kado

Yukihiro Shibata

Fumihiro Inoue

Yasuharu Kikuchi

Yasushi Goho

Syunichi Iwanari

Kevin Tien

Akinori Kobayashi

Kouichi Tsubouchi

Yoko Ishida

Satoshi Hirohata

A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

Methods and systems are provided for operating a neuromorphic system for generating neuron and synapse activities. The method includes: preparing at least one digital timer in the neuromorphic system, each of the at least one digital timers including multi-bit digital values; generating time signals using the at least one digital timer; emulating an analog waveform of a neuron spike; updating parameters of the neuromorphic system using the time signals and the current values of the parameters; presetting, using a processor, the digital values of the at least one digital timer to initial values when the spike input is provided to the node; and updating, using the processor, the digital values of the at least one digital timer with a specified amount when there is an absence of a spike input to the node.

Timing sequence for digital STDP synapse and LIF neuron-based neuromorphic system

A two-stage gated-diode sense amplifier includes a first transistor connected to an input node, a second transistor connected to a boost node, the input node and a setting line, a first inverter including a third transistor connected to a power supply voltage (VDD), a first output corresponding to the first inverter and the setting line, and a fourth transistor connected to ground, the first output and the setting line, a fifth transistor connected to the first output, the first transistor and the boost node, and a second associated with a second output corresponding to the second inverter, the second inverter including a sixth transistor connected to VDD, the second output and the first output, and a seventh transistor connected to ground, the second output and the first output.

Two-stage gated-diode sense amplifier

A method and system are provided for updating synapse weight values in neuromorphic system with Spike Time Dependent Plasticity model. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.

LUT based synapse weight update scheme in STDP neuromorphic systems

Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.

Digitial STDP synapse and LIF neuron-based neuromorphic system

A sense amplifier includes a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line. The sense amplifier further includes a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line.

Sense amplifiers for wider I/O memory device

A method and system are provided for updating a neuron membrane potential in a spike time dependent plasticity model in a Neuromorphic system. The method includes approximating a shape of an analog spike signal from an axon input using a hardware-based digital axon timer. The method further includes generating a first intermediately updated neuron membrane potential value from a current axon timer value, a current synapse weight value and a current neuron membrane potential value using a first look-up table and an accumulator. The method also includes generating a second intermediately updated neuron membrane potential value with a leak decay effect using a second look-up table and the first intermediately updated neuron membrane potential value. The method additionally includes generating a final updated neuron membrane potential value based on a comparison of the second intermediately updated neuron membrane potential value with a neuron fire threshold level using a comparator.

LUT based neuron membrane potential update scheme in STDP neuromorphic systems

Digital STDP synapse and LIF neuron-based neuromorphic system

A method includes applying a first voltage to a source of a first p-channel FET connected in series with a second p-channel FET, applying a second voltage, lower than the first voltage, to a source of a third p-channel FET connected in series with a fourth p-channel FET, applying a third voltage, lower than the first and second voltages, to a source of a second n-channel FET connected in series with a first n-channel FET, drains of the second p-channel FET, the fourth p-channel FET, and the first n-channel FET connect at a connection point including an output terminal for outputting an output signal, and outputting one of the first voltage, the second voltage, and the third voltage from the output terminal based on input signals inputted to corresponding gates of the first p-channel FET, the third p-channel FET, the fourth p-channel FET, and the second n-channel FET.

Dual power rail cascode driver

A level shifter and dynamic random-access memory that includes a first output terminal and a second output terminal. A first voltage or a third voltage is outputted from the first output terminal. A second voltage or a fourth voltage is outputted from the second output terminal. The second voltage is lower than the first voltage. The third voltage is lower than the first voltage and higher than the second voltage. The fourth voltage is lower than the first voltage and higher than the third voltage.

Cascode complimentary dual level shifter

An embodiment includes a tie-off circuit includes multiple field effect transistors (FETs), and a node isolation circuit that is connected to a first output node and a second output node of the tie-off circuit. The node isolation circuit consists of a first FET with a third output node and a second FET with a fourth output node. The second output node includes a logical LO node and is coupled to a gate of the first FET and generates a TIE HI output.

Node isolation for protection from electrostatic discharge (ESD) damage

Embodiments relate to electrostatic discharge (ESD) protection. One embodiment includes a tie-off circuit including a multiple field effect transistors (FETs), a first internal node, a second internal node, a first output node and a second output node. A node isolation circuit is connected to the first output node and the second output node of the tie-off circuit. The node isolation circuit includes a first FET with a third output node and a second FET with a fourth output node. The third output node and the fourth output node are electrically isolated from the first internal node and the second internal node.

Tie-off circuit with output node isolation for protection from electrostatic discharge (ESD) damage

A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.

Time division multiplexed limited switch dynamic logic

A dynamic logic circuit includes a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal. A second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal.

A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

Growing community of inventors

Kyoto, Japan

Yutaka Nakamura