Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Yutaka Nabeshima

Shingo Fukamizu

Hisashi Ogawa

Masanori Fukumoto

Tokuhiko Tamaki

Yasunori Yamamoto

Yuichi Hirofuji

Masaoki Kajiyama

Hidenori Iwadate

Tomohiro Matsunaga

Takashi Katsuyama

A placement configuration of MIM type capacitance elements comprises a group of first capacitance elements in which the first capacitance elements as the MIM type capacitance elements are placed in tandem and a group of second capacitance elements in which the second capacitance elements as the MIM type capacitance elements are placed in tandem, wherein the group of first capacitance elements and the group of second capacitance elements are alternately placed in parallel with each other with an equal interval therebetween.

Placement configuration of MIM type capacitance element

A semiconductor integrated circuit relating to one aspect of the present invention includes a power transistor, at least one or more of first metal patterns functioning as a first electrode of the power transistor and at least one or more of second metal patterns functioning as a second electrode of the power transistor formed in an interlayer insulation film on the transistor, at least one or more of first busses electrically connected to a corresponding first metal pattern of the at least one or more of the first metal patterns, a single second bus electrically connected to the at least one or more of second metal patterns, and a contact pad provided to each of the at least one or more of first busses and the single second bus.

Semiconductor integrated circuit providing for wire bonding directly above an active circuit region, and manufacturing method thereof

A semiconductor device includes a semiconductor substrate including at least one of a circuit and a circuit element, and an inductor element having a coil axis extending in a direction parallel to a main surface of the semiconductor substrate and disposed adjacent to the main surface. A main direction of a magnetic field induced by passing a current through the inductor element is parallel to the main surface.

Semiconductor device

An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.

Spiral planar inductor and manufacturing method thereof

The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right above the first metal layer, and contact pads provided on the first and second buses. The contact pad has a probe testing region and a bonding region.

Semiconductor integrated circuit device and fabrication method for the same

A semiconductor integrated circuit includes a power transistor formed on a semiconductor substrate, a plurality of first metal patterns and a plurality of second metal patterns which are formed right above the power transistor and function as a first electrode and as a second electrode of the power transistor, respectively, a plurality of first buses each electrically connected with, of a plurality of first metal patterns, a corresponding first metal pattern, a plurality of second buses each electrically connected with, of a plurality of second metal patterns, a corresponding second metal pattern, wherein one contact pad is provided to each of a plurality of first buses and a plurality of second buses.

Semiconductor integrated circuit and method for manufacturing the same

In a method of manufacturing a variable capacitance diode according to the present invention, a mask is formed on a semiconductor substrate of a first conductive type having a low impurity concentration, a semiconductor region of the first conductive type having an intermediate impurity concentration is formed on the semiconductor substrate by means of ion implantation via an opening portion of the mask, a semiconductor region of a second conductive type having a high impurity concentration is formed in the semiconductor substrate on a surface side thereof relative to the semiconductor region of the first conductive type having the intermediate impurity concentration via the same opening portion of the mask, and the semiconductor region of the first conductive type having the intermediate impurity concentration and the semiconductor region of the second conductive type having the high impurity concentration are activated by applying a heat treatment to the semiconductor substrate. In a variable capacitance diode according to the present invention, a structure in which an annular contact layer of a first conductive type is formed in a periphery of a semiconductor region of a second conductive type having a high impurity concentration constitutes each of a plurality of units and the plurality of units is disposed in an array.

Method of manufacturing variable capacitance diode and variable capacitance diode

A method of fabricating a semiconductor device is disclosed. The method comprises the steps of: forming a multi-layer film comprising two or more kinds of layers; performing first etching for patterning said multi-layer film under a first etching condition; and performing second etching for forming irregularities in the side faces of said patterned multi-layer film under a second etching condition.

Method of fabricating a memory device with a multilayer insulating film

A dry etching method for dry etching a silicon oxide film or a multilayer oxide film thereof which enables formation of contact window to good dimensional precision and with stable etching configuration in the process of film etching at submicron level. A compound gas containing a C element or S element or Cl element, and F element (e.g., CF.sub.4) is used as a principal gas, and a compound gas containing a C element and two or more of H elements (e.g., CH.sub.2 F.sub.2) as an additive gas is used, in the process of dry etching silicon oxide film or a multilayer film thereof. By using principal and additive gases having good step coverage of deposit produced by plasma reaction, it is possible to eliminate any etching residue and form contact windows having stable etching configuration and good dimensional accuracy in the process of film etching at submicron level. By using a compound gas containing a greater number of H element atoms than C element atoms, the deposit on the etching side wall can be a soluble one having a low F element content, such as (C.sub.x H.sub.y)n polymer, and can be readily removed through after-etching washing.

Growing community of inventors

Osaka, Japan

Yutaka Nabeshima