Texas Instruments Corporation

Other

Yutaka Komai

Tsukasa Ooishi

Shigeki Tomishima

Hiroaki Tanizaki

Roger D Norwood

Duy-Loan T Le

Scott E Smith

Charles J Pilch

Daniel B Penny

Carl W Perrin

A synchronous semiconductor memory device in a test mode of operation receives an external clock signal and is controlled by an internal clock adjustment circuit producing an internal clock signal of high frequency to provide write and read operations. A clock cycle converter circuit included in the internal clock adjustment circuit included in the internal clock adjustment circuit produces the internal clock signal by performing a hierarchical exclusive-OR operation on a specific pair of two of eight clock signals successively delayed in phase with respect to the external clock signal.

Synchronous semiconductor integrated circuit device capable of test time reduction

To provide a semiconductor device fuse, which does not damage the lower layer when it is cut by irradiation with a laser beam. In forming a fuse,by forming an electroconductive thin film on the surface of a semiconductor substrate and patterning it, a cut part,is constituted by installing an expanding part,in a narrow-width part,, and the cut part,is cut by irradiation with a laser beam. Even if scattering of the intensity of the laser beam and scattering of the irradiation position occur, no damage occurs in the lower layer, and an electrical element can be formed even at the position directly under the fuse,. The cut part,preferably has a circular shape.

Fuse for semiconductor device and semiconductor device

A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signal (*CLK) in response to the second logic state. The second clock signal has a frequency at least twice a frequency of the first clock signal. An address counter (221) is coupled to receive one of the first and second clock signals. The address counter produces a sequence of address signals corresponding to the one of the first and second clock signals. An array of memory cells is arranged to produce a sequence of data bits corresponding to the sequence of address signals. A logic circuit (235, 239, 240) is coupled to receive the sequence of data bits. The logic circuit produces a logical combination of the sequence of data bits.

Internal clock multiplication for test time reduction

A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.

Testing and repair of wide I/O semiconductor memory devices designed for

Growing community of inventors

Ibaraki, Japan

Yutaka Komai