Elpida Memory, Inc.

Other

Ps4 Luxco S.a.r.l.

Yutaka Kagaya

Hidehiro Takeshima

Masachika Masuda

Toshio Sugano

Masamichi Ishihara

Susumu Hatano

Akihiko Iwaya

Fumitomo Watanabe

Keiyo Kusanagi

Akihiko Hatasawa

Hajime Takasaki

Koya Kikuchi

Noriou Shimada

A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Stacked semiconductor device and fabrication method for same

A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.

Semiconductor device having a first conductive member connecting a chip to a wiring board pad and a second conductive member connecting the wiring board pad to a land on an insulator covering the chip and the wiring board

A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant.

Semiconductor device including a first land on the wiring substrate and a second land on the sealing portion

Semiconductor deviceincludes wiring substrateincluding wiringand wiringin predetermined patterns, semiconductor chipsandwhich are mounted on wiring substratewith electrodes electrically connected to wiringof wiring substratevia wiresand, first sealing bodymade of an insulative resin which is formed on a part of wiring substrateand which covers semiconductor chipsandand wiresand, a plurality of connecting connection padsprovided on the top surface of first sealing body, a plurality of connecting wireswhich extend from the surface of wiring substrate, on which semiconductor chipsandare mounted, to the top surface of first sealing bodyvia the side surfaces of first sealing body, and which electrically connect wiringof wiring substrateand the plurality of connecting connection padsand second sealing bodymade of an insulative resin which covers the plurality of connecting wires

Semiconductor device and manufacturing method of the same

The semiconductor device is made up of two wiring boards, a semiconductor chip, and a sealing part. The two wiring boards are spaced apart, and a semiconductor chip is mounted so as to span the two wiring boards. The semiconductor chip includes a predetermined circuit and a plurality of electrode pads on one side thereof. The wiring board includes a plurality of connection pads on a semiconductor chip-mounting face, and a plurality of lands on the opposite side thereof. The land is electrically connected to a corresponding connection pad. An external terminal is formed on each of the lands. Further, the electrode pad formed in the semiconductor chip is electrically connected to the corresponding connection pad of the wiring board. Moreover, the semiconductor chip, the semiconductor chip mounting face of the wiring board, and the side faces of the wiring board are covered with the sealing part.

Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof

Stacked semiconductor device

A semiconductor device includes: an insulating tape having a device hole and a plurality of holes; a plurality of leads formed on one surface of the tape and extending at one end into the device hole and at the other end into the holes; a semiconductor chip having a plurality of electrodes on a main surface thereof, being connected with the leads extending into the device hole; an encapsulant formed of an insulating resin, the leads and a predetermined portion of the tape; bump electrodes provided on one surface of the leads; slits provided in the tape between the encapsulant and the bump electrodes and extending along a column of the bump electrodes; and a warp prevention reinforcement made of an insulating film and formed over the tape; wherein the semiconductor chip and the bump electrodes are connected to one and the same surface side of the leads.

Semiconductor device including a semiconductor chip formed on an insulating element such as a tape, and including an improved insulating arrangement

In a semiconductor device in which a plurality of substrates each mounting a semiconductor chip are stacked, one ends of the leads formed on the substrates are connected to the semiconductor chip and the other ends thereof are connected to connection terminals of the substrates. At least one of the leads are branched into two or more in the vicinity of the connection terminals, and one ends of the branched leads are connected to the connection terminals. A technique for sorting good products is performed in a state in which the chips are mounted on the substrates.

Semiconductor device and its manufacturing method

A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips are mounted on a substrate in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate Each chip has a plurality of pads which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads that are located on the side of central part on a specified plane of the substrate and control-use pads of control signals that are also placed on the center side of the substrate The pad array also includes input/output pads that are disposed so that these are on the peripheral side on the surface of substrate

Semiconductor device

A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips are mounted on a substrate in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate . Each chip has a plurality of pads which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads that are located on the side of central part on a specified plane of the substrate , and control-use pads of control signals that are also placed on the center side of the substrate . The pad array also includes input/output pads that are disposed so that these are on the peripheral side on the surface of substrate

Growing community of inventors

Tokyo, Japan

Yutaka Kagaya