Hitachi, Ltd.

Texas Instruments Corporation

Yutaka Itou

Hidetoshi Iwai

Toshiyuki Sakuta

Takumi Nasu

Tomohiro Suzuki

A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8. Since the coupling impedance between shield wiring 1 and substrate 7 (due almost solely to the electrostatic capacitance Css) is large, and coupling impedance between Vss wiring 2 and substrate 7 (due almost solely to the junction capacitance D) is low, the noise caused by variations in the potential of substrate 7 is transferred to shield wiring 1, while it is not appreciably transferred to Vss wiring 2.

Growing community of inventors

Ohme, Japan

Yutaka Itou