Hitachi, Ltd.

Micron Technology Incorporated

Elpida Memory, Inc.

Sumitomo Chemical Company, Limited

Other

Toppan Printing Co., Ltd.

Nippon Electric Co., Ltd.

Konami Digital Entertainment Co., Ltd.

Hitachi Chemical Company, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Texas Instruments Corporation

Nippon Telegraph and Telephone Corporation

Victor Company of Japan, Limited

Namco Limited

Ricoh Printing Systems, Ltd.

Yutaka Ito

Yuan He

Takayuki Nakakawaji

Hiroshi Sasaki

Mitsuyoshi Shoji

Shigeki Komatsuzaki

Keiichiro Abe

Mitsuyoshi Shouji

Hiroyuki Matsumoto

Adrian J Drexler

Masayoshi Nomura

Takahiko Kozaki

Shinobu Gohara

Kenichi Kawashima

Junichirou Yanagi

Kiyoshi Aiki

Kaoru Aoki

Yoshiro Riho

Hidetoshi Iwai

Takeshi Hashimoto

Takuya Nakanishi

Hiroshi Tani

Mina Ishida

Brandi M Jones

Masao Inaba

Toshikazu Narahara

Masatoshi Wakagi

Yoshiyuki Tanabe

Shuji Imazeki

Atsushi Sekine

Masaya Muranaka

Masanobu Hanazono

Fumio Nakano

Heigo Ishihara

Hideaki Kato

Kunihiro Tamahashi

Shigeo Takeuchi

Juichi Arai

Fuminori Ishikawa

Tadashi Yamamoto

Hiroshi Takahashi

Akio Mukoh

Yasuhiro Yoshimura

Koji Sato

Yoshishige Endo

Kiyoshi Nakai

Setsuo Kobayashi

Katsuhiro Kambara

Tomoyuki Hamada

Hiromitsu Tokisue

Toshiyuki Sakuta

Yoshifumi Mochida

Takeshi Okubo

Kishiro Iwasaki

Atsushi Morihara

Makoto Mori

Masaru Morohashi

Kenji Toda

Tetsu Umeda

Hisashi Morooka

Takao Uematsu

Yukiko Ikeda

Yasuhiro Yamashita

Nobuyuki Ishii

Koji Sonoda

Takahiro Daikoku

Teruaki Mitsuya

Yoshitaka Tadaki

Kenzo Fukuyoshi

Hiroyoshi Kokaku

Masamichi Ishihara

Jun Nakagawa

Nobuyoshi Hoshi

Toshitsugu Takekuma

Yukihide Suzuki

Tetsuya Hamaguchi

Atsushi Kakuta

Shizuo Zushi

Tsuneaki Kawanishi

Tadashi Iizuka

Kazuya Ito

Akio Idei

Morihito Miyagi

Makoto Kurosawa

Akira Sato

Mitsuhiro Shoda

Kohei Yamashita

Katsumi Tamura

Yasushi Takagi

Takumi Nasu

Yukihiro Kimura

Motoo Akagi

Shigeo Suzuki

Takao Shimizu

Mineo Mizukami

Ken'ichi Kawashima

Ryuichi Kaji

Yoshinari Suzuki

Mina Amo

Masaaki Imamura

Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

Apparatuses and methods for multiple row hammer refresh address sequences

A laminated film is provided which can prevent transmission of water vapor at a high level, and can suppress prevention of dark spots over a long period of time when used as a supporting substrate of an electronic device such as an organic EL element, and a laminated film is provided comprising at least a gas barrier layer and an inorganic polymer layer laminated on a resin substrate, wherein the arithmetic average height (Sa) of a surface of the inorganic polymer layer is 20 nm or less, and the NHgas generation amount per unit mass of the inorganic polymer layer when the laminated film comprising the inorganic polymer layer is accommodated in a sample chamber, and the interior of the sample chamber is heated at 85&#xb0; C. for 1 hour while the humidified air at 25&#xb0; C. and 85% RH is flown through the sample chamber is 5000 mass ppm or less.

Laminated film and process for manufacturing the same

Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

Techniques for reducing row hammer refresh

Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number. The filter circuit further includes a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses responsive to the output signal from the control circuit being not enabled.

Apparatus and methods for triggering row hammer address sampling

Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array.

Multi channel memory with flexible code-length ECC

Apparatuses for executing interrupt refresh are described. An example apparatus includes: memory banks, a sampling timing generator circuit, bank sampling circuits and a command state signal generator circuit that provides a command state signal responsive to a command. Each memory bank includes a latch that stores an address for interrupt refresh. The sampling timing generator circuit receives an oscillation signal and provides a trigger signal of sampling the address. Each bank sampling circuit is associated with a corresponding memory bank. Each bank sampling circuit provides a sampling signal to the latch in the corresponding memory bank responsive to the trigger signal of sampling the address. The sampling timing generator circuit provides the trigger signal of sampling the address, responsive, at least in part, to the command state signal, and the latch stores the address, responsive, at least in part, to the at least one trigger signal of sampling the address.

Apparatus and methods for refreshing memory

Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.

Apparatuses for refreshing memory of a semiconductor device

A laminated film containing a gas barrier layer and an inorganic polymer layer laminated on a resin substrate, wherein a Y value calculated from a transmission electron microscope image of a cross section of the inorganic polymer layer by the following procedures (a) to (d) is 0.220 or less: (a) Calculating a standard deviation (&#x3c3;) of the contrast of an electron beam-unirradiated part of the inorganic polymer layer; (b) Dividing an electron beam-irradiated part of the inorganic polymer layer into twenty parts having a film thickness equal in a film thickness direction, and calculating a standard deviation (an: standard deviation of ndivision, n=1&#x2dc;20) of the contrast of each divided part; (c) Calculating Xn (n=1&#x2dc;20) of each divided part from the expression (1): Xn=&#x3c3;n/&#x3c3; (n=1&#x2dc;20) . . . (1); and (d) A standard deviation of X3 to X18 is defined as Y.

Laminated film and process for manufacturing the same, as well as method for analyzing laminated film

Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.

Methods for adjusting memory device refresh operations based on memory device temperature, and related memory devices and systems

A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.

Semiconductor device

An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

Redundancy area refresh rate increase

A liquid crystal display device is provided with a display substrate, an array substrate, a liquid crystal layer sandwiched between the display substrate and the array substrate, and control circuitry. The display substrate includes a touch sensing line. The array substrate includes a common electrode having a constant potential, a first insulating layer provided under the common electrode, a pixel electrode provided under the first insulating layer, a second insulating layer provided under the pixel electrode, a conductive line electrically connected to the common electrode under the second insulating layer, a third insulating layer provided under the conductive line, and a first active element and a second active element provided under the third insulating layer and electrically connected to the pixel electrode.

Liquid crystal display device

A laminated film includes a flexible base material, a first thin film layer formed on at least one of surfaces of the base material, and a second thin film layer formed on the first thin film layer, and the first thin film layer contains a silicon atom (Si), an oxygen atom (O) and a carbon atom (C), the second thin film layer contains a silicon atom, an oxygen atom and a nitrogen atom (N), and the first thin film layer and the second thin film layer are formed by using glow discharge plasma.

Laminated film and flexible electronic device

Growing community of inventors

Tokyo, Japan

Yutaka Ito