Mitsubishi Denki Kabushiki Kaisha

Ps4 Luxco S.a.r.l.

Micron Technology Incorporated

Honda Giken Kogyo Kabushiki Kaisha

Elpida Memory, Inc.

Fdk Corporation

Mitsubishi Electric Engineering Company, Limited

Mitsubihsi Denki Kabushiki Kaisha

Chemgenesis Incorporated

Farnex Incorporated

Yutaka Ikeda

Nakaba Kaiwa

Kyoji Yamasaki

Hiroki Fujisawa

Tetsuaki Okahiro

Takashi Takahashi

Takashi Itou

Takeshi Kajimoto

Akio Nakayama

Akihiro Fujii

Yoshinori Inoue

Hiroshi Akamatsu

Mikio Sakurai

Mitsunori Tsujino

Osamu Kitade

Kenji Tokami

Jun Nakai

Masami Miyamoto

Yukiko Maruyama

Motoko Hara

Tsuyoshi Nishimura

Ichiro Hijikuro

Kiyoshi Hironaka

Yoshinao Fujimura

Kazuhiro Sakemi

Jun Yamashita

Shigeru Yamaoka

Tetsuya Aono

Hiroto Tokutome

Kenichirou Suzuki

Kouichi Nagase

Koichi Nagase

Yoshinori Mizugai

Takeshi Nishimura

Satoshi Imuta

Yasuhiro Hiroki

A device includes an amplifying circuit having first and second input terminals and an output terminal, a ground terminal, a variable resistance circuit, and a resistance selecting circuit coupled in series to the variable resistance circuit between the output terminal and the ground terminal. The resistance selecting circuit includes a first node coupled to the second input terminal, a plurality of resistors coupled in series to each other and a plurality of gate circuits each coupled between the first node and one end of a corresponding one of the resistors.

Device having internal voltage generating circuit

A transformer in which the high-voltage and low-voltage coils are easily laminated when they are alternately laminated in their axial directions, improving power efficiency. The transformer includes: a high-voltage coil including a wire wound around a cylindrical winding drum of a bobbin which is provided with flanges on both ends of the winding drum; a low-voltage coil formed of a flat plate member having an open ring shape, the low-voltage and high-voltage coils being alternately laminated in their axial directions; and a cover member which has a ring plate shape and is coaxially laminated on an outside of a laminate in an axial direction. The low-voltage coil is between the high-voltage coil and the cover member, and a wall portion protruding in the axial direction from the bobbin of the high-voltage coil and a wall portion protruding in the axial direction of the cover member are alternately disposed.

Transformer

A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands

Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands

A device, comprising an output terminal; an output circuit coupled to the output terminal and having an adjustable impedance; and an impedance adjustment circuit adjusting stepwise the adjustable impedance so as to head toward a first reference impedance. The impedance adjustment circuit changes the adjustable impedance by a first amount when the adjustable impedance is within a first range, and changes the adjustable impedance by a second amount when the adjustable impedance is out of the first range. The first amount is smaller than the second amount.

Semiconductor device

A common mode choke coil includes a quadrilateral core; first and second core coversdisposed opposite to each other on the upper and lower surfaces of the coreso as to cover the outer periphery of the core; and rectangular copper wireswound on the opposite side portions of the coreof the first and second core covers. The second core coveris disposed on a component-mounting face. The first and second core coversinclude a pair of linear portions surrounding the corresponding opposite sides of the corewhich linear portions constitute winding portions. The lower surface of the second core coverhas a pedestal portionwhich protrudes more toward the component-mounting face than the winding portions, and extends out along the component-mounting face in a direction perpendicular to axis lines of the winding portions. The lower face at the tip of the protruding part of the pedestal portionhas seat faceson which parts of the rectangular copper wiresdrawn from the winding portionstoward the component-mounting face are provided as mounting terminals. Tip portions of the rectangular copper wiresare bent upward from the seat facesat the edge of the tip of the protruding part of the pedestal portion.

Common-mode choke coil

The present invention relates to a liquid crystal compound that can be used as a base for injection formulations. The present invention provides an amphipathic compound having the following general formula (I): wherein X and Y each denotes a hydrogen atom or together denote an oxygen atom, n denotes an integer from 0 to 2, m denotes the integer 1 or 2, and R denotes a hydrophilic group generated by removal of one hydroxyl group from any one selected from the group consisting of glycerol, erythritol, pentaerythritol, diglycerol, triglycerol, xylose, sorbitol, ascorbic acid, glucose, galactose, mannose, dipentaerythritol, maltose, mannitol, and xylitol; as well as a base for injection formulations and depot formulation comprising the same.

Low-viscosity liquid crystal compound

A semiconductor device includes a signal generating circuit that generates an impedance adjustment command signal which indicates at least one of initiation and termination of an impedance adjustment. The semiconductor device outputs an output signal in synchronism with the impedance adjustment command signal.

A device includes a first circuit and an adjustment circuit. The adjustment circuit performs an adjustment on impedance of the first circuit. The adjustment circuit discontinues the adjustment on impedance while the first circuit is in an activated state.

A semiconductor memory device includes an internal voltage generation circuit controlling an internal voltage supplied to an internal circuit in accordance with a reference voltage, a reference voltage generation circuit generating the reference voltage, a plurality of signal terminals for transmitting and receiving a signal to and from an outside of the semiconductor memory device, and a reference voltage change indication circuit for indicating a change of the reference voltage on the basis of a binary input signal to each of the signal terminals with respect to the reference voltage generation circuit during a test.

Semiconductor memory device having internal circuit screening function

In a test mode, read data is output from a memory array with each of N latch circuits in an output circuit being set to an operating state under the control of a latency setting circuit. Thus, the data transmission period can be set shorter in the test mode than in a normal data reading operation, and a time required for testing the read data in the test mode is shortened.

Semiconductor memory device permitting early detection of defective test data

Consuming current must be reduced in each operation state of a semiconductor device which operates in synchronized with an external clock signal. However, in each operation state, for satisfying the stability of an operation and a speedup, the suppression of consuming current has been performed under difficult circumstances. For solving this problem, a clock generation circuit generating an internal clock signal based on an external clock signal is activated during a specific time period when a clock synchronization circuit is in a state of inactivation.

A DLL circuit includes a counter control circuit. The counter control circuit includes an inverter, a NAND gate, a shift register, a clocked inverter, and a NOR gate. When a reset signal RST of an H level, or a smallest address signal CMIN indicating the smallest value of the address is input, the counter control circuit forces a signal REV to be switched to an H level and generates a counter control signal ADD and a signal EN of an H level, whereby the counter enters a force up mode. As a result, the delay clock CLKD can be set in phase with a reference clock CLK stably.

DLL circuit that can prevent erroneous operation

A DLL circuit includes a fine delay circuit including a first inverter circuit, a second inverter circuit and delay units. The first inverter circuit has an output terminal connected to an output terminal of the second inverter and the first and second inverters are configured of inverters of different sizes. A phase comparator compares a delay clock's phase with a reference clock's phase and a result of the phase comparison is referred to to count addresses which are in turn used to selectively drive the inverters configuring the first and second inverter circuits, to allow the fine delay circuit to output a signal having a phase between signals having therebetween a phase difference of a fixed amount. Thus the clock's phase can be adjusted with high precision.

Delay locked loop circuit capable of adjusting phase of clock with high precision

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Tokyo, Japan

Yutaka Ikeda