Renesas Electronics Corporation

Yutaka Igaku

Yukitoshi Tsuboi

Daisuke Kawakami

Hideo Nagano

Naotaka Kubota

Hiroshi Nagaoka

Shinichi Shibahara

Yasuhiro Yamakoshi

Yusuke Matsunaga

A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.

Semiconductor apparatus and diagnostic test method

A control systemaccording to the present invention is mounted on a moving object. The control systemincludes: an observing devicewhich transmits observation result data indicating an observation result of surroundings of the moving object; a first control instruction devicewhich transmits first control data indicating the control contents determined based on the observation result data; a movement control devicewhich controls movement of the moving object; and a relay devicewhich relays the first control data transmitted from the first control instruction device, to the movement control device. When a second control instruction devicewhich transmits second control data indicating the control contents determined based on the observation result data is provided to the control system, the relay devicetransmits the second control data instead of the first control data, to the movement control device

Control system, relay device and control method

A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

Semiconductor device, diagnostic test, and diagnostic test circuit

Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor deviceaccording to the present invention includes a plurality of CPU corestoeach including a scan chain, and a diagnostic test circuitthat performs a scan test for the plurality of CPU corestoby using the scan chain of the CPU core. The diagnostic test circuitperforms a scan test for each of the plurality of CPU corestoin a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Growing community of inventors

Tokyo, Japan

Yutaka Igaku