Sanyo Electric Co., Ltd.

Yutaka Hirakoso

Kazuhiro Kimura

Takahiko Masumoto

Shigeaki Hayashibe

Yasuji Saito

Toshiyuki Ozawa

Masaaki Taira

Shizuka Ishimura

Munehiro Suka

Hiroshi Kaneko

An AM receiving circuit is disclosed which comprises an intermediate frequency amplifying unit that generates an intermediate frequency signal from a broadcast wave signal received by an antenna to amplify and output the intermediate frequency signal; an AGC (Automatic Gain Control) unit that sets gain of the intermediate frequency amplifying unit depending on electric field intensity of the broadcast wave signal; and an AM detecting unit that detects the intermediate frequency signal output from the intermediate frequency amplifying unit, wherein the AM receiving circuit comprises a sound quality compensating unit including: a filter unit that extracts a predetermined frequency band of the audio signal; an amplifying unit that boosts or attenuates the audio signal in the predetermined frequency band extracted from the filter unit; and a controlling unit that controls filter characteristics of the filter unit and sets a boosting function or an attenuating function of the amplifying unit, depending on the electric field intensity of the broadcast wave signal.

AM receiving circuit

A signal processing circuit is disclosed which comprises: an attenuating unit that attenuates a demodulated signal acquired by detecting a received signal; a detecting unit that detects a first signal indicating intensity of the demodulated signal; and an attenuation rate setting unit that sets an attenuation rate of the attenuating unit based on the first signal, wherein the attenuation rate setting unit sets the attenuation rate of the attenuating unit depending on: at least one signal of a second signal indicating a change in an envelope curve acquired based on an intermediate frequency signal of the received signal and a third signal indicating electric field intensity acquired based on the intermediate frequency signal; and the first signal.

Signal processing circuit comprising an attenuating unit, a detecting unit, and an attenuation rate setting unit

A signal processing circuit for a tuner has a detector band pass filter for extracting a carrier of an intermediate frequency signal, a frequency counter for counting, based on a clock signal, a frequency of a carrier of the intermediate frequency signal which passes through the detector band pass filter, and an intermediate frequency variation signal outputting section for outputting an intermediate frequency variation signal based on a difference between the counted frequency and a frequency of the clock signal. Based on the intermediate frequency variation signal, a frequency selection characteristic of an intermediate frequency band pass filter, a signal detector, an adjacent interference detector, or an S-meter-band pass filter are controlled. In this manner, even when a carrier frequency of an intermediate frequency signal input from a tuner varies, the frequency selection characteristic of the intermediate frequency band pass filter, signal detector, adjacent interference detector, and S-meter-band pass filter can be suitably controlled.

Signal processing circuit for tuner which applies signal processing based on variation in frequency of intermediate frequency signal

An AM receiver circuit comprises an IF intensity detection section which detects intensity of a carrier wave of an IF signal and outputs an IF signal carrier wave intensity signal in accordance with the detected intensity. The IF intensity detection section extracts the carrier wave frequency component of the IF signal using a BPF, and converts the extracted intensity of the IF signal carrier wave intensity into a direct current signal using an integrator, to thereby obtain the IF signal carrier wave intensity signal. A sound compensation section, which serves to compensate sound quality of an audio signal output from an AM detection section, performs sound quality compensation based on the IF signal carrier wave intensity signal when the received field intensity is low. In this manner, appropriate sound quality compensation can be performed even when the received broadcast wave field intensity is low.

AM receiver circuit performing sound quality compensation of AM detection output signal

Data counters and perform a counting operation which is synchronized with the respective timing of receiving multiplex data from a VICS data broadcasting station and a D-GPS data broadcasting station. While receiving the multiplex data from the VICS data broadcasting station, based on an output C of the data counter and a BIC detection output BP, block synchronization is detected. When the broadcasting station is switched from the VICS data broadcasting station to the D-GPS data broadcasting station, an output C of the data counter is selected in response to a control signal CONT and block synchronization is detected based on an output C and an output BP. Further, an output C is always inputted to the block counter. Thus, even while receiving the multiplex data from the D-GPS data broadcasting station, frame synchronization of the multiplex data of the VICS data broadcasting station is detected without causing miscounting.

Synchronous circuit of FM multiplex broadcasting receiver

A receiver receives FM multiplex broadcast data of both RDS and DARC systems by using one front end. A BIC detection circuit ( ) detects a block identification code (BIC) included in received data. A coincidence/non-coincidence detection circuit ( ) judges whether or not a BIC detection timing is correct and emits a coincidence/non-coincidence pulse. A forward protection circuit ( ) counts a frequency of outputs of non-coincidence pulses and retains an established synchronous condition until the counted value exceeds a predetermined value. Then, a forward protection control circuit ( ) inhibits the forward protection circuit from performing a count operation while a search is performed for selecting a station. Also, a rearward protection circuit ( ) counts a frequency of outputs of coincidence pulses and establishes a synchronous condition when the counted value reaches a predetermined value. Further, a rearward protection control circuit ( ) inhibits the rearward protection circuit from performing a count operation while a search is performed.

Synchronous circuit for FM multiple broadcast receiver

Superimposed FM data is demodulated to digital data. A synchronism reproducing circuit (data block detecting section) detects the front of blocks in the digital data to generate a block head signal (a station change timing signal), which is supplied to a control section of a station selecting microcomputer. When a station selecting key requests a change of the received station, station data corresponding to a requested station is supplied to the control section (a station selecting control section). When the block head signal is inputted after requesting the change of the station, the control section begins to output station change data to a PLL frequency synthesizer in order to change the frequency signal in a front end. This prevents a latter part of a block in received superimposed FM data from being NG data.

FM radio receiver and signal processing device used therein

In accordance with the operation of an operating section 14, a control section 12 performs a reception control operation and demodulates a signal passing through a band pass filter 7 for extracting a multiplex signal using a multiplex signal demodulating section 8 when receiving a broadcast signal. A block synchronization circuit 16 of a synchronization circuit 9 carries out block synchronization processing on the demodulated signal. When block synchronization is established, a synchronization determination signal is supplied to a detecting section DET and the detecting section DET determines that a broadcasting station whose radio waves are currently being received is a multiplex broadcasting station.

FM multiplex broadcast receiving circuit for detecting presence or

In multiplex FM broadcasting, a digital signal is composed of a frame which consists of a predetermined number of blocks in the vertical direction, a block consisting of a predetermined number of bits in the horizontal direction and having a horizontal parity (error correcting code) for correcting errors in the horizontal direction and a vertical parity for correcting errors in the vertical direction. The block also has a control bit for determining whether the error correction in the horizontal direction is to be carried out only once. A decoding identification detector (20) detects the content of the control bit, a controller (12) controls the re-writing of the digital signal into a frame buffer (13) after the error correction of the digital signal in the vertical direction by an error corrector (14). The controller (12) also controls the provision of the digital signal stored in the buffer (13) to the error corrector (14) according to the content of the control bit, determining whether the second error correction in the horizontal direction is to be carried out.

Digital signal processing for controlling error correction based on the

An SI judging circuit in a service detecting section detects a service identification code included in a block included in received superimposed FM data. When the block represents an unnecessary service, the SI judging circuit generates a predetermined service detecting signal, which is supplied to a station selecting microcomputer. A user operates a station selecting key to request the change of the broadcasting station. When the change is requested, and also the service detecting signal indicating that the service included in the received block is not needed is supplied to the station selecting microcomputer by the SI judging circuit, a control section of the station selecting microcomputer outputs station data corresponding to the requested station to a PLL synthesizer, and then the frequency signal (tuning frequency) is changed at a front end. This enables data received during a period for receiving blocks for unnecessary services to be NG, and can prevent data of blocks including necessary services from being NG.

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Koga, Japan

Yutaka Hirakoso