Mitsubishi Denki Kabushiki Kaisha

Other

Yutaka Arima

Toshiaki Hanibuchi

Ichiro Tomioka

Hiroki Ui

Yoshikazu Kondo

Kunihiko Hara

Yasuyuki Endo

A metal oxide semiconductor transistor includes a semiconductor substrate; a source area formed in a device area of the semiconductor substrate; a drain area formed in the device area; a gate layer formed on and across the device area between the source area and the drain area; a control gate layer; and a diffusion area formed in the device area between the gate area and the control gate area. The control gate layer has a first part including a first end of the control gate layer and a second part including a second end of the control gate layer. The first part is formed on the device area between the source area and the gate layer. The first end is disposed so that there is a gap between the first end and an edge of the device area.

Metal oxide semiconductor transistor

A semiconductor image pickup device includes a pixel array having pixels arranged in a matrix. Each pixel includes a photodiode that converts an optical signal into an electrical signal, and a transistor connected to a charge accumulation section of the photodiode. A buffer is additionally provided. This buffer controls the transistor of the pixels using a lower control power supply voltage than a power supply voltage of the pixel array.

Semiconductor image pickup device

A product-sum calculation apparatus is provided for cumulatively adding up respective products of first input data and second input data. There is further provided a product-sum calculation unit integrated circuit apparatus including the product-sum calculation apparatus, and a cumulative adder. In the product-sum calculation apparatus, a barrel shifter shifts the first input data by a predetermined number of bits based on the second input data, and an adder adds the shifted data outputted from the barrel shifter and inputted through a first input terminal thereof, and data inputted through a second input terminal thereof. A register temporarily stores data outputted from the adder, outputs a stored data to the adder through the second input terminal of the adder, and outputs the stored data through an output terminal. Further, there is provided a multiplexer for selecting either one of third input data inputted through a first input terminal thereof, and data inputted through a second input terminal thereof. Accordingly, the product-sum calculation apparatus calculates a product of the first input data and the second input data, calculates a sum of a calculated product and the third input data, and outputs a calculated sum from the output terminal.

Product-sum calculation apparatus, product-sum calculating unit

A self-organizable neural network expressing unit includes a plurality of neuron units electronically expressing nerve cell bodies, and a plurality of synapse expressing units electronically expressing synapses for coupling neuron units through programmed coupling strengths represented by synapse load values, and a control circuit for supplying a pattern of random number data as an educator data. When the pattern of random number data is generated, the neural network expressing unit carries out correction of synapse load values as in a learning mode of operation using the pattern of random number data as an educator data. The memorized internal states in the neural network expressing unit is reinforced based on a faded memory thereof, and the synapse load values are precisely maintained for a long time, resulting in a reliable neural network expressing unit.

Neural network expressing apparatus including refresh of stored synapse

Arithmetic units are supplied with instructions from a control unit in common through an instruction broadcast bus. Each of the arithmetic units includes a process data input port, an address data input port, a process data output port and an address data output port. Address data appearing on the address ports specify addresses of a local memory. Each of the arithmetic units reads corresponding numeric data from the local memory and executes arithmetic processing in accordance with the instruction supplied from the control unit through a computing element group and a register group. In each arithmetic unit, it is possible to specify addresses of the local memory independently of each other. Each unit include circuitry for omitting an arithmetic operation on data read from the local memory when the read out data is negligible.

Numerical arithmetic processing unit

A synapse expressing unit includes a capacitor for storing a synapse load value information in a form of electric charges, and a refresh control circuit for remedying the change in the amount of the electric charges stored in the capacitor. The refresh control circuit includes a comparator for comparing a potential at an electrode of the capacitor and a reference potential, and a drive circuit responsive to the comparator for recovering the electric charges of the capacitor through charge pumping operation. The synapse load value information is refreshed, and therefore a neural network circuit device reliably operating for a long time duration is provided.

Data synapse expressing unit capable of refreshing stored synapse load

An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circuits, and a plurality of buffer circuits. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines. Each synapse representing unit includes a learning control circuit which derives synapse load change value data in accordance with predetermined learning rules in response to a first axon signal Si and a second axon signal Sj, a synapse load representing circuit which corrects a synapse load in response to the synapse load change valued data and holds the corrected synapse load value Wij, a first synapse coupling operating circuit which derives a current signal indicating a product Wij.multidot.Si from the synapse load Wij and the first axon signal Si and transfers the same to a first dendrite signal line, and a second product signal indicating a product Wij.multidot.Sj from the synapse load Wij and the second axon signal Sj and transfers the same onto a second dendrite signal line.

Neural network integrated circuit device having self-organizing function

A neutral network representing apparatus includes a plurality of neuron expressing units and a plurality of synapse load expressing units. Each of the synapse load expressing units couples two neuron expressing units through a synapse load which is specific thereto. The synapse load of the synapse load expressing unit is adjusted in accordance with a prescribed learning rule in learning of the neural network representing apparatus. This learning rule includes a learning coefficient which defines the amount of a synapse load to be changed in a single learning cycle. This learning coefficient is set according to a spatial or physical distance between two neurons expressed by two neuron expressing units which are coupled by a synapse load expressing unit. The learning coefficient is provided by a monotone decreasing function of the distance between the two neurons.

Neural network representing apparatus having self-organizing function

An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines.

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Hyogo, Japan

Yutaka Arima