Nec Corporation

Renesas Electronics Corporation

Fuji Xerox Co., Ltd.

Other

Kabushiki Kaisha Toshiba

Kyocera Corporation

Renesas Technology Corp.

Nec Electronics Corporation

Oki Electric Industry Co., Ltd.

Ibiden Company Limited

Fujitsu Microelectronics Limited

Oki Semiconductor Co., Ltd.

Fujitsu Corporation

Fujikura Limited

Fujitsu Semiconductor Limited

Yutaka Akiyama

Yasutaka Nakashiba

Kanji Otsuka

Tohru Kawai

Tamotsu Usami

Tsuneo Ito

Yuko Tanba

Daisuke Iguchi

Yoichi Sato

Akira Yoshino

Akihiro Shimomura

Chihiro Ueda

Saya Shimomura

Masayuki Furumiya

Kenji Sasaki

Yoshinori Arai

Ryota Yamamoto

Kenichi Furuta

Fumiaki Fujii

Shigeru Yamamoto

Osamu Koyasu

Hitoshi Tsunashima

Keisuke Yanagisawa

Fumio Mizuno

Munekazu Takano

Kazuhiro Takimoto

Minoru Uwai

Takeshi Koyama

Yasushi Yoshikawa

Ayuta Yamada

Osamu Kawai

Masahiro Yoshida

Masahito Ohue

Tatsuya Nagasawa

Hidemitsu Mori

Toshiyuki Shou

Saburo Yokokura

Toru Ishizuka

In response to request signals transmitted from a terminal, a server generates prediction information relating to pharmacokinetics of a peptide. The server then transmits the prediction information to the terminal.

Information processing device, information processing method, recording medium recording information processing program, and information processing system

An information processing device configured to present a virtual space at a display mounted on the head of a user, the information processing device inputs detection information from a sensor that detects movement of the head of the user. The information processing device generates the virtual space including a body image representing at least a part of a body of the user in response to the detection information. The information processing device inputs correction information from a device operated to perform correction of an angle in a pitch direction of the head of the user. The information processing device corrects a pitch direction angle employed when presenting the virtual space at the display based on the correction information. The information processing device presents the virtual space at the display with the corrected pitch direction angle.

Information processing device, information processing method, and non-transitory computer readable storage medium storing an information processing program

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Semiconductor device and method of manufacturing the same

A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

Semiconductor device

An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer.

Semiconductor device and manufacturing method thereof

A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.

Semiconductor device and method of writing/reading entry address into/from semiconductor device

A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.

Multi chip semiconductor device

A printed circuit board includes a ground layer, a power source layer, a signal wiring layer, an insulating layer and an electromagnetic radiation suppressing member. The power source layer is provided to be opposed to the ground layer. The signal wiring layer transmits a signal in a predetermined frequency domain. The insulating layer insulates the ground layer, the power source layer and the signal wiring layer from one another. The electromagnetic radiation suppressing member is provided to cover a circumferential edge of the insulating layer. The electromagnetic radiation suppressing member has a negative dielectric constant and a positive magnetic permeability in a frequency domain including the predetermined frequency domain.

Printed circuit board

A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memoriesincluding basic cellsarranged in a cluster, the basic cellincluding a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memorieslocated along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibusincluding a through-via, an arbitrary one of the basic cellsis directly accessed through the multibusfrom the controller chip so that truth value data is written therein, and whereby the arbitrary basic cellis switched to a logic circuit as conjugate.

Memory/logic conjugate system

To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate, second conductivity type first wellsanddisposed on a surface layer of the semiconductor substratewith a predetermined interval between them, a first conductivity type second welldisposed between the first wellsandon the surface layer of the semiconductor substrateand having an impurity concentration higher than that of the semiconductor substrate, a first conductivity type third wellat least disposed below the second wellin the semiconductor substrateand having an impurity concentration higher than that of the semiconductor substrateand lower than that of the second well, and a first conductivity type fourth wellat least disposed below the third wellin the semiconductor substrateand having an impurity concentration higher than that of the semiconductor substrateand lower than that of the second well

Method of fabricating semiconductor device with a high breakdown voltage between neighboring wells

An image sensor array is provided with: first and second CCD image sensors that output a plurality of first and second signal voltages from first and second output terminals, respectively; a switch circuit selectively connecting one of the first and second output terminals to a signal voltage output terminal; and a timing generator circuit responsive to a basic clock generating first and second control signals and switch control signals. First and second control signals control generation of the first and second signal voltages, respectively. The switch control signals are used for controlling the switch circuit. The timing generator circuit controls the first and second CCD image sensors so that the first and second CCD image sensors alternately output the first and second signal voltages. The timing generator circuit controls the switch circuit to alternately output from the signal voltage output terminal one of the first and second signal voltages.

Image sensor array architecture for improved resolution switching

Growing community of inventors

Kawasaki, Japan

Yutaka Akiyama