Nec Corporation

Nec Toppan Circuit Solutions, Inc.

Nec Tokin Corporation

Yutaka Akimoto

Hideo Kikuchi

Toshiyuki Kaneko

Hirofumi Nakamura

Takayuki Inoi

Katsuhiro Yoshida

Sadamu Toita

Hideki Kikuchi

Keiji Nagano

Kazuhiro Kinoshita

Kiyohiko Kaiya

A sheet-shaped capacitor for storing electrical charges of large capacities, and to assure facilitated manufacture, cost reduction and improved reliability, and a method for manufacturing the capacitor. The capacitor includes a dielectric film, formed on a first major surface of a metal plate, an electrically conductive high polymer layer, formed on a first major surface of the dielectric film, and an electrically conductive layerformed on a first major surface of the electrically conductive high polymer layer, such as by copper plating. A cathode electrodeis led out from the electrically conductive layeron the side electrically conductive high polymer layer

Sheet-shaped capacitor and method for manufacture thereof

Occurrence of EMI is reduced without a sharp increase of the manufacturing cost by suppressing a common mode current stably. There is provided a disclosed printed-circuit board being adapted such that a width of an outer edge section of a T-shaped pattern is widened so as to surround a recessed section with a frame-shaped additional electric conductor by electrically connecting the frame-shaped additional electric conductor with the T-shaped pattern making up a ground pattern so as to close the recessed section.

Printed-circuit board, coaxial cable, and electronic device

A layout compaction method adapted to be embodied in computer program product and adapted for compacting a circuit layout having a plurality of layers on which moving objects form layer patterns, wherein the moving objects comprising components and wires. The method assumes a graph problem under condition which prevent the compacted result from violation of the design rule, and then, solves the graph problem to determine a moving order, a moving direction, and a moving distance of each component for moving the components to thereby perform the compacting the circuit layout. After that, the method moves each component according to the moving order, the moving direction and the moving distance to obtain a compacted circuit layout.

COMPACTING METHOD OF CIRCUIT LAYOUT BY MOVING COMPONENTS USING MARGINS AND BUNDLE WIDTHS IN COMPLIANCE WITH THE DESIGN RULE, A DEVICE USING THE METHOD AND A COMPUTER PRODUCT ENABLING PROCESSOR TO PERFORM THE METHOD

In a graphic layout compaction system for compacting a layout where components and routes are placed on a two-dimensional space, a terminal graph generator prepares terminal graph data indicative of terminal graphs having component terminals as nodes. The terminal graph generator calculates, as a movement amount for allowing a first component terminal to come near a second component terminal, a movement limit area within which the first component terminal can move in any directions towards the second component terminal in consideration of a route bandwidth interposed therebetween. A component compactor moves the first component terminal on a position where the first component terminal is not interfered with the movement limit area. A rerouting unit shapes routes into shaped routes having configurations including oblique parts to reroute the shaped routes in a space between the first and the second component terminals.

Graphic layout compaction system capable of compacting a layout at once

Growing community of inventors

Tokyo, Japan

Yutaka Akimoto