Renesas Electronics Corporation

Yuta Yanagitani

Ken Shibata

Shinji Tanaka

Kiyotada Funane

A semiconductor device having a high degree of freedom of layout has a first part AR, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP) for the plurality of wells PW is arranged on one side so as to interpose the ARin a Y-axis direction, and a common power feeding region (ARN) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP) for the PW wells, a p-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR, and a plurality of MIS transistors are correspondingly formed.

Semiconductor device and method of manufacturing semiconductor device

The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.

Growing community of inventors

Kanagawa, Japan

Yuta Yanagitani