Fujitsu Corporation

Showa Denko K.k.

Yuta Toyoda

Tomohiro Inoue

Shinya Hiramoto

Shun Ando

Masahiro Maeda

Koji Hosoe

Akio Tokoyoda

Masatoshi Aihara

Makoto Suga

Yuichiro Ajima

Ryosaku Inamura

Shigeki Itou

Instruction-execution processors each execute a first instruction. A control processor converts a second instruction to be emulated into the first instruction, and enters the converted first instruction into the instruction-execution processors. In a parallel-execution period, each instruction-execution processor executes a writing-access instruction or a reading-access instruction to a memory, suspends writing of data into the memory caused by the writing-access instruction, and retains an execution history of the writing-access instruction and the reading-access instruction. The control processor selects one of instruction-execution processors in which addresses of the memory access instructions conflict with each other, causes the selected instruction-execution processor to complete the writing of the data into the memory, enters first instructions to be executed in a next parallel-execution period into the selected instruction-execution processor, and causes another instruction-execution processor to re-execute first instructions executed by the other instruction-execution processors in the parallel-execution period, in the next parallel-execution period.

Apparatus and method to emulate a sequence of instructions via parallel processors

An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory.

Arithmetic processing unit, and method of controlling arithmetic processing unit

An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.

Information processing apparatus, parallel computer system, and control method for controlling information processing apparatus

A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.

Memory controller, information processing apparatus, and method of controlling memory controller

An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.

Arithmetic processing device, information processing device, and control method of arithmetic processing device

A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.

Parallel computer, node apparatus, and control method for the parallel computer

The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.

Information processing apparatus and control method of information processing apparatus

A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.

Memory controller, information processing apparatus, and method of controlling information processing apparatus

A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.

Parallel computer system, control method of parallel computer system, information processing device, arithmetic processing device, and communication control device

A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.

Parallel computer system, crossbar switch, and method of controlling parallel computer system according to selective transmission of data via ports of the crossbar switch

A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases.

Parallel computer system, data transfer device, and method for controlling parallel computer system for performing arbitration

A magnetic storage medium includes a seed layer made of non-magnetic and amorphous Co&#x2014;Cr&#x2014;W, an intermediate layer having a crystalline structure, which is made of a non-magnetic material on the seed layer and has a c-axis oriented in a thickness direction of the seed layer in a hexagonal close-packed structure, and a recording layer made of mainly a magnetic material on the intermediate layer and having information magnetically recorded therein.

Magnetic storage medium and information storage device

A perpendicular magnetic recording medium includes a nonmagnetic seed layer, a nonmagnetic intermediate layer provided on the nonmagnetic seed layer, and a perpendicular recording layer provided on the nonmagnetic intermediate layer. The nonmagnetic seed layer includes a first seed layer made of an amorphous material, and a second seed layer provided between the first seed layer and the nonmagnetic intermediate layer and made of a material having a fcc structure. The amorphous material includes at least one element selected from a group consisting of Ta, W, Nb, Mo, Zr and alloys thereof which include at least one of Ta, W, Nb, Mo and Zr as a main component exceeding 50 at. %.

Perpendicular magnetic recording medium and magnetic storage apparatus

A perpendicular magnetic recording medium includes a nonmagnetic seed layer, a nonmagnetic intermediate layer provided on the nonmagnetic seed layer, and a perpendicular recording layer provided on the nonmagnetic intermediate layer. The nonmagnetic seed layer includes a first seed layer made of a Ni alloy having a fcc structure, and a second seed layer provided between the first seed layer and the nonmagnetic intermediate layer and made of a Ni alloy having a fcc structure. A content of one or more elements other than Ni within the Ni alloy forming the second seed layer and having a Goldschmidt radius greater than that of Ni is larger than a content of one or more elements other than Ni within the Ni alloy forming the first seed layer and having a Goldschmidt radius greater than that of Ni.

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Kawasaki, Japan

Yuta Toyoda