Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Kabushiki Kaisha Toyota Jidoshokki

Kabushiki Kaisha Toyota Chuo Kenkyusho

Sumitomo Riko Company Limited

Denso Corpora Tion

Yusuke Yamashita

Satoru Machida

Jun Saito

Yuichi Takeuchi

Yasushi Urakami

Masaru Senoo

Yasuhiro Hirabayashi

Katsumi Suzuki

Jun Okawara

Shuhei Mitani

Akitaka Soeno

Katsuhiro Kutsuki

Hiroshi Hosokawa

Yukihiko Watanabe

Takayuki Hirose

Takahide Sugiyama

Shinji Suzuki

Ryota Suzuki

Tadashi Misumi

Keita Kataoka

Takehiro Kato

Yasuhiro Ebihara

Yoshifumi Yasuda

Masahiro Sugimoto

Motoaki Okuda

Atsushi Minagata

Toru Onishi

Kensaku Yamamoto

Atsuya Akiba

Atsushi Onogi

Hiromichi Kinpara

Youngshin Eum

Masato Ogasawara

Aiko Kaji

Yasuaki Takenaka

Tsuyoshi Yamamoto

Tatsuji Nagaoka

Katsunori Danno

Hitoshi Yoshikawa

Hiroki Miyake

Jun Kobayashi

Tomohiro Nakamura

Koichi Nishikawa

Hirokuni Akiyama

Shingo Komura

Ryuji Oide

Mikiya Kurita

Takashi Kuno

Yutaro Taguchi

Kouji Eguchi

Yuki Murakami

Teruaki Kumazawa

Shimpei Mune

Masato Noborio

Yuto Kurokawa

Tomoaki Tachibana

Masakazu Okada

Masatoshi Tsujimura

Shinichirou Miyahara

Junichi Uehara

A switching element includes a semiconductor substrate, a gate insulating film, and a gate electrode that is disposed inside the trench. The semiconductor substrate further includes: an n-type source region, a p-type body region, an n-type drift region, a p-type first electric field reduced region, and a p-type connection region. When a permittivity of the connection region is ε (F/cm), a critical electric field strength of the connection region is Ec (V/cm), an elementary charge is e (C), an area density of p-type impurity when viewed in a plan view of the connection region located below the trench is Q (cm), Q>ε*Ec/e.

Switching element

A semiconductor device includes a semiconductor substrate having an active region in which a main switching element structure is formed, a current sense region in which a sense switching element structure is formed, and a peripheral region located around the active region and the current sense region. The semiconductor substrate is a 4H-SiC substrate having an off angle in a <11-20> direction. The current sense region is disposed in a range where the active region is not present when viewed along the <1-100> direction.

Semiconductor device

A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region.

A silicon carbide semiconductor device includes an electric field relaxation layer disposed in a drift layer. The electric field relaxation layer includes a first region having a second conductivity type and disposed at a position deeper than trenches, and a second region having the second conductivity type and disposed between the adjacent trenches to be away from a side surface of each of the adjacent trenches. Each of the first region and the second region is made of an ion implantation layer. The electric field relaxation layer further includes a double implantation region in which the first region and the second region overlap with each other, and the electric field relaxation layer has a peak of a second conductivity type impurity concentration in the double implantation region.

Silicon carbide semiconductor device with overlapping electric field relaxation regions and method of manufacturing the same

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

Silicon carbide semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate, a top electrode in contact with a top surface of the semiconductor substrate, a bottom electrode in contact with a bottom surface of the semiconductor substrate, and an oxide film in contact with the top surface of the semiconductor substrate. The semiconductor substrate includes an element region and an outer peripheral region. The element region is a region where the top electrode is in contact with the top surface of the semiconductor substrate. The outer peripheral region is a region where the oxide film is in contact with the top surface of the semiconductor substrate, and is located between the element region and an outer peripheral end surface of the semiconductor substrate. The element region includes a semiconductor element connected between the top electrode and the bottom electrode. The outer peripheral region includes surface high-voltage-breakdown regions, deep high-voltage-breakdown regions, and a drift region.

Semiconductor device with surface and deep guard rings

A semiconductor device includes a cell section having a plurality of gate structures, and an outer peripheral section surrounding the cell section. The cell section includes a semiconductor substrate, the plurality of gate structures, a first electrode and a second electrode. The cell section and the outer peripheral section includes a protective film made of a material having a thermal conductivity lower than that of the first electrode. The protective film extends from the outer peripheral section to an outer edge portion of the cell section adjacent to the outer peripheral section and covers a portion of the first electrode adjacent to the outer peripheral section.

Semiconductor device having cell section with gate structures partly covered with protective film

A semiconductor device includes a semiconductor element having a substrate, a drift layer, a base region, a source region, trench gate structures, an interlayer insulating film, a source electrode, and a drain electrode. The substrate is made of silicon carbide. The drift layer is disposed on the substrate and has an impurity concentration lower than the substrate. The base region is made of silicon carbide and disposed on the drift layer. The source region is made of silicon carbide having an impurity concentration higher than the drift layer. Each trench gate structure has a gate trench, a gate insulating film, and a gate electrode. The interlayer insulating film covers the gate electrode and the gate insulating film. The source electrode is in ohmic-contact with the source region. The drain electrode is disposed on a rear surface of the substrate.

Silicon carbide semiconductor device and method for manufacturing same

A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Silicon carbide semiconductor device and manufacturing method of silicon carbide semiconductor device

A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

Manufacturing method of semiconductor device including semiconductor element of inversion type

A SiC semiconductor device includes a main cell region and sense cell region being electrically isolated by an element isolation portion. The SiC semiconductor device includes a substrate, a first impurity region, a first current dispersion layer, first deep layers, a second current dispersion layer, a second deep layer, a base region, a trench gate structure, a second impurity region, first electrodes and a second electrode. The second impurity region, the first electrodes, and the second electrode are disposed at the main cell region and the sense cell region to form a vertical semiconductor element. The vertical semiconductor element allows a current flowing between the first electrode and the second electrode through a voltage applied to the gate electrode. The spacing interval between the deep layers at the element isolation portion is shorter than or equal to a spacing interval between the deep layers at the main cell region.

Silicon carbide semiconductor device

A semiconductor device includes a semiconductor substrate comprising an upper surface and a lower surface, an upper electrode provided on the upper surface, and a lower electrode provided on the lower surface. The semiconductor substrate includes, in a planar view, a first section including a center of the semiconductor substrate and a second section located between the first section and a peripheral edge of the semiconductor substrate. The first and second sections each comprise a MOSFET structure including a body diode. The MOSFET structure in the first section and the MOSFET structure in the second section are different from each other such that a forward voltage drop of the body diode in the first section with respect to a current density is higher than a forward voltage drop of the body diode in the second section with respect to the current density.

A semiconductor device includes; a schottky diode; a semiconductor substrate that includes a first surface and a second surface opposite to the first surface; a schottky electrode that is placed on the first surface and schottky-contacts to the semiconductor substrate; a first electrode placed on the schottky electrode; and a second electrode that is placed on the second surface and is connected to the semiconductor substrate. The schottky electrode is made of a metal material that is a columnar crystal; and a content of carbon on the schottky electrode is less than 6&#xd7;10cmin at least a part of an area of the schottky electrode.

A power storage apparatus has a case accommodating an electrode assembly, and a release valve present in the wall of the case. The electrode assembly includes electrodes. A shielding member is arranged between the inner surface of the wall and the end surface of the electrode assembly. A point located in a center of the case in a front view of the case taken in the stacking direction of the electrodes and located in a center of a dimension of the electrode assembly in the stacking direction is a center point, and a region surrounded by a plane connecting the center point and a contour of the pressure release valve at a shortest distance is a three-dimensional region. The shielding member includes a shielding portion that entirely covers a cross section of the three-dimensional region along the end face of the electrode assembly.

Power storage apparatus

Semiconductor device including saturation current suppression layer

Growing community of inventors

Nagakute, Japan

Yusuke Yamashita