Yamaha Corporation

Yusuke Yamamoto

Yasuyuki Muraki

Masao Noro

Toshio Maejima

Akira Usui

Ichiro Futohashi

Masamitsu Yamamura

Junji Torii

Lenichi Takeuchi

Ritsuo Matsushita

The present invention is directed to a power control circuit for reducing wasteful power consumption of an electronic apparatus such as a digital signal processor. More specifically, a preferred embodiment of the present invention includes a processing detecting device that detects occurrence of an index indicative of a start of execution of a process by the electronic apparatus, a processing termination detecting device for detecting a termination of the processes, and a power control device that responds to the detection of the termination of the process for reducing the power consumption by at least one circuit element of the electronic apparatus for a time period after the termination of the processing, and until the next occurrence of the index indicative of another start of execution of a process.

Power saving control by predetermined frequency slot timing signal based start index and halt instruction termination signal

A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address. A sampled data input and output device performs an input and output operation every sampling period, the input and output operation comprising generating plural kinds of offset addresses corresponding, respectively, to the plural kinds of signal processing and not overlapping with each other, generating at least one write address or read address for the sampled data for each of the plural kinds of signal processing by modifying the basic address by at least one of the offset addresses corresponding to each of the plural kinds of signal processing, and delivering the generated at least one write address or read address to the storage device.

Digital signal processor and digital signal processing method

A digital signal processor which can reduce the electric power consumption in a fine manner according to the contents of processing to be executed. An arithmetic device performs arithmetic operations according to operation instructions. A storage device stores plural sets of the operation instructions and control instructions corresponding to respective ones of the operation instructions and indicative of kinds of processings to be executed according to the respective ones of the operation instructions. A control device is disposed to receive an externally supplied control signal indicative of kinds of processings to be executed by the digital signal processor, and reads out the operation instructions and the control instructions corresponding to the respective ones of the operation instructions and renders the arithmetic device inoperative when a kind of processing indicated by the control signal and a kind of processing indicated by each of the control instructions read out do not coincide with each other.

Digital signal processor

A digital signal processor performs signal processing corresponding to a designated one of a plurality of sampling frequencies. A slot changing device carries out changeover of slots at a frequency equivalent to a common multiple of the plurality of sampling frequencies. A slot cycle setting device sets a slot cycle formed of the slots corresponding in number to a sampling period determined by the designated one of the plurality of sampling frequencies. An executing device executes routines corresponding to the slots forming the slot cycle, with a repetition period determined by the set slot cycle, to thereby perform signal processing corresponding to the designated one of the plurality of sampling frequencies in a time-discrete manner.

Plural sampling frequency signal processing by performing designated routines during sub-multiple time slots of each period

An asynchronous signal input apparatus includes a memory device which writes data that are input at a predetermined frequency, in response to a write signal, and reads data in response to a read signal. A data quantity measuring device measures a data quantity representing a quantity of data stored in the memory device. A read signal generating device generates the read signal at a frequency that varies depending upon the measured data quantity. A sampling frequency conversion apparatus comprises the memory device, data quantity measuring device, and read signal generating device employed in the asynchronous signal input apparatus. Further, the read signal generating device includes a converter which performs non-linear conversion on the data quantity measured by the data quantity measuring device. An interpolation information producing device produces interpolation information to be used for data generated from the memory device, based on the data quantity to which the non-linear gain is given by the converter. An interpolation device interpolates data that are read from the memory device in response to the read signal, based on the produced interpolation information.

Asynchronous signal input apparatus and sampling frequency conversion apparatus

An analog-digital converter includes a .DELTA..SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA..SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA..SIGMA. modulator includes at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator. Each switched-capacitor integrator is configured using a CMOS differential amplifier which is configured by a CMOS operational amplifier and at least one amplitude-limiting circuit. The amplitude-limiting circuit is configured by two PMOS transistors and two NMOS transistors which are connected in parallel in a diode-connection manner; and this circuit is provided to limit amplitude in output of the CMOS differential amplifier by stabilizing its operating point.

CMOS differential amplifier for a delta sigma modulator applicable for

An analog-digital converter comprises a .DELTA. .SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA. .SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA. .SIGMA. modulator comprises at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator. Each switched-capacitor integrator is configured using a CMOS differential amplifier which is configured by a CMOS operational amplifier and at least one amplitude-limiting circuit. The amplitude-limiting circuit is configured by two PMOS transistors and two NMOS transistors which are connected in parallel in a diode-connection manner; and this circuit is provided to limit amplitude in output of the CMOS differential amplifier by stabilizing its operating point.

Analog-Digital converter using delta sigma modulation digital filtering,

A digital filter performs a predetermined arithmetic operation on input digital data inputted thereto in time-series manner by the predetermined first sampling period to thereby generate output digital data corresponding to a second sampling frequency which is N (where N denotes an integral number) times larger than the predetermined first sampling frequency. This digital filter provides a synchronizing signal generating circuit and an operation control circuit. The synchronizing signal generating circuit detects the predetermined first sampling period of the input digital data to thereby generate a synchronizing signal having the second sampling frequency. The operation control circuit is activated by its internal clock which is asynchronous with the input digital data. This operation control circuit starts to perform its operation processes when the synchronizing signal is supplied thereto, thereafter it terminates the operation processes when a predetermined step number is completed.

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Hamamatsu, Japan

Yusuke Yamamoto