Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Yusuke Tokunaga

Shiro Dosho

Shiro Sakiyama

Takashi Morie

Akinori Matsumoto

Yasuyuki Doi

Toru Iwata

Takashi Hirata

Makoto Hattori

Masaya Sumita

Kazuo Matsukawa

Yoshito Date

Yukihiro Sasagawa

Seiji Watanabe

Kazuaki Sogawa

Tetsuro Ohmori

Hiroshi Koshida

Kurumi Nakayama

Hirofumi Nakagawa

Hideki Yoshii

Yasuhiro Tatewaki

Kaori Nishikawa

A solid-state imaging device includes: a pixel unit that outputs a pixel signal corresponding to an amount of incident light; an A/D converter that performs A/D conversion on the pixel signal; and a D/A conversion circuit that generates a reference signal to be used by the A/D converter. The D/A conversion circuit includes a first buffer circuit that outputs a base voltage VTOP for generating the reference signal, and the first buffer circuit includes a differential pair circuit including a first transistor and a second transistor, and a suppression circuit that suppresses a variation in the base voltage by canceling out a characteristic difference between the first transistor and the second transistor.

Solid-state imaging device and camera

An imaging device includes a pixel array, a first converter, a second converter, a first ramp signal generation circuit that is disposed closer to the first converter than to the second converter and supplies a first ramp signal to the first converter and the second converter, a first connection line having one end connected to an output terminal of the first ramp signal generation circuit and including a portion extending away from an input terminal of the first converter in a path from the one end to the other end of the first connection line, and a second connection line having one end connected to the other end of the first connection line and the other end connected to the input terminal and including a portion extending closer to the input terminal in a path from the one end to the other end of the second connection line.

Imaging device and camera

An amplifier circuit has: a first amplifier circuit, including a chopper circuit amplifying a first differential signal input between first and second input terminals to output a second differential signal; and a second amplifier circuit amplifying the second differential signal to output a single-ended signal. The second amplifier circuit includes: a first circuit including first and second transistors, the first circuit being connected to the first amplifier circuit so that the second differential signal input into gates of these transistors, the first circuit converting the second differential signal to a current flowing into a first node connected to the first transistor and a current flowing into a second node connected to the second transistor; and a second circuit negatively feeding back a voltage at the second node so that the difference in voltage between these nodes is reduced. The second amplifier circuit outputs the single-ended signal from the first node.

Amplifier circuit

An inverting amplifier includes an input terminal, an output terminal, a PMOS transistor, another PMOS transistor, an NMOS transistor, another NMOS transistor, and a clamp circuit. The PMOS transistors are connected in series between a supply voltage and an output terminal. The NMOS transistors are connected in series between a ground voltage and the output terminal. The clamp circuit is connected to the gate of the other PMOS transistor and the gate of the other NMOS transistor. The clamp circuit includes a switch, a capacitor, another switch, and another capacitor. At least one of the gate of the PMOS transistor and the gate of the NMOS transistor is connected to the input terminal.

Inverting amplifier, integrator, sample hold circuit, ad converter, image sensor, and imaging apparatus

A switched capacitor circuit includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; an inverting amplifier including a second input terminal connected to the second terminal; a capacitor including a third terminal, a fourth terminal, and a fifth terminal which is connected to an output terminal; a capacitor including a seventh terminal, a sixth terminal connected to the second output terminal, and an eighth terminal connected to the third terminal; a capacitor connected in series between the second terminal and the output terminal; and an offset compensation unit which outputs an offset voltage having a value of a short-circuit voltage of the inverting amplifier to the fourth terminal and the seventh terminal.

Switched capacitor circuit and method for driving the same

A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal.

Switched capacitor circuit and drive method thereof

An A/D converter includes: an A/D converter circuit that causes a dissipation current (I) having dependence on an input voltage (V); and a counteracting current generation circuit controlled based on an output digital value (D) provided from the A/D converter circuit to generate a counteracting current (I) that is a dissipation current for reducing the dependence of the dissipation current (I) on the input voltage.

A/D converter, image sensor, and digital camera

An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.

Analog-digital conversion circuit and method for driving the same

An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.

Reference frequency generation circuit, semiconductor integrated circuit, and electronic device

An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.

In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p&#xd7;q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.

Coupled ring oscillator and method for initializing the same

The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

Charge pump circuit

A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Phase adjustment circuit

A selection section () selects a step voltage, among a plurality of step voltages (SV, SV, SV, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV, SV, SV, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section () amplifies the step voltage selected by the selection section (). An output section () outputs the step voltage amplified by the amplifier section () as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

Digital/analog converter circuit

A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Growing community of inventors

Hyogo, Japan

Yusuke Tokunaga