Hitachi, Ltd.

Other

Renesas Technology Corp.

Yusuke Takeuchi

Yasuyuki Kojima

Minehiro Nemoto

Nobuyasu Kanekawa

Seigou Yukutake

Takayuki Iwasaki

Kazuhisa Takami

Tatsuya Saito

Atsuo Watanabe

Masaru Kokubo

Hiroki Yamashita

Takashige Baba

Mitsuaki Horiuchi

Satoru Isomura

Kazuo Okado

Yasuo Shima

Katsuhiro Furukawa

Seigo Yukutake

Yoshiaki Yuyama

Sakae Miki

Keizo Yabuta

Koki Sakai

Shinichi Tanabe

Takayuki Iwasakii

Atuko Kenmoku

A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.

Signal transmit-receive device, circuit, and loopback test method

The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N written on the pseudo-frequency-dividing-ratio-register and the value N written on the pseudo-over-sampling-ratio-register are converted through a user interface into the frequency dividing ratio N by the conversion circuit and the converted result is written in the frequency-dividing-ratio-register

Over-sampling A/D, D/A converter

A circuit region on a main surface of an SOI substrate, and a isolating region defined by insulating isolation trenches and are connected by a wiring resistor, or a diffused resistor in the SOI substrate. The isolating region and an intermediate region are connected by a wiring resistor, or a diffused resistor in the SOI substrate. Furthermore, a circuit region on a main surface of an SOI substrate, and a isolating region defined by insulating isolation trenches and are connected by a wiring resistor, or a diffused resistor in the SOI substrate. The isolating region and an intermediate region are connected by a wiring resistor, or a diffused resistor in the SOI substrate. As a result, distribution of voltage applied between the circuit regions and by the wiring resistors or the diffused resistors to can increase the withstand voltage of a semiconductor integrated circuit.

Semiconductor integrated circuit device and manufacturing method thereof

In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.

Line interface circuit and information communication apparatus using it

A sending data buffer for holding sending data temporarily and transmitting the data to an echo canceler section is installed between a sending section and an echo canceler section of an echo canceler integrated circuit included in a subscriber line circuit of an integrated service digital network. The sending data buffer is operated in a shift register mode during a sending training mode, and operated in FIFO (first in-first out) mode during a sending/receiving training mode. Also, an adjustment function of the delay amount corresponding to the use setting is added.

Semiconductor integrated device

Disclosed is a DMA controller incorporated in a data processor, comprising a plurality of channels and a control circuit for overseeing these channels. Each of these channels has registers for storing transfer parameters (address and byte count), registers for storing control parameters (status and command), data assembler circuit, and a channel control circuit that controls these registers and data assembler circuits. The channel control circuit in each channel simultaneously processes transfer parameters for an increased data transmission rate and a reduction of the internal processing unit work load.

Single chip communication data processor with direct memory access

Growing community of inventors

Hachioji, Japan

Yusuke Takeuchi