Panasonic Intellectual Property Management Co., Ltd.

Yusuke Sakata

Mitsuyoshi Mori

Yutaka Hirose

Ryohei Miyagawa

Hiroshi Masuda

Hitoshi Kuriyama

Yoshihisa Kato

Akito Inoue

Yoshihiro Sato

Hideyuki Arai

Toru Okino

Manabu Usuda

Yuki Sugiura

Kentaro Nakanishi

Yoshiyuki Ohmori

Tatsuya Kabe

Hisashi Aikawa

Motonori Ishii

Hiroyuki Doi

Masafumi Tsutsui

A light detector is configured such that a light receiving portion having APDs and a peripheral portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral portion has an n-type MISFET provided at a p-well and an n-well provided to surround entire side and bottom portions of the p-well.

Light detector

A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.

A photodetector includes: at least one avalanche photodiode including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first transistor connected to the first semiconductor layer and including a channel of the second conductivity type that has polarity opposite to polarity of the first conductivity type; and a second transistor connected to the first semiconductor layer and including a channel of the first conductivity type.

Photodetector, photodetector array, and drive method comprising a second transistor including a channel of first conductivity type and a first transistor including a channel of second conductivity type that has polarity opposite to polarity of the first conductivity type

A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p&#x2212; type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p&#x2212; type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p&#x2212; type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p&#x2212; type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p&#x2212; type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.

Photodiode, photodiode array, and solid-state imaging device

An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material.

Solid-state imaging device

A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.

A solid-state imaging device includes a substrate of P type and a wiring layer. The substrate includes: a first semiconductor region disposed on a first principle surface and extending in a direction from the first principal surface toward the second principal surface; a second semiconductor region disposed between the second principal surface and the first semiconductor region and connected to the first semiconductor region; a P type semiconductor region disposed between the second principal surface and the second semiconductor regions of two pixels; and a pixel isolation region disposed inside the substrate, between the first semiconductor regions of the two pixels. The second semiconductor region and the P type semiconductor region form an avalanche multiplication region.

A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line.

A solid-state imaging device includes: pixels arranged in a matrix, a semiconductor substrate; a first electrode formed above the semiconductor substrate for each of the pixels; a photoelectric conversion film formed on the first electrode, for photoelectric conversion of light into signal charge; a charge accumulation region formed in the semiconductor substrate for accumulating the signal charge generated through the photoelectric conversion in the photoelectric conversion film; a contact plug for electrically connecting the first electrode and the charge accumulation region in a corresponding pixel; a high-concentration impurity region formed on a surface of the charge accumulation region, in a region in contact with the contact plug; a surface impurity region formed on the surface of the charge accumulation region, in a region not in contact with the contact plug; and a low-concentration impurity region formed between the high-concentration impurity region and the surface impurity region.

A solid-state imaging device includes: an epilayer; pixel electrodes; a photoelectric converting film formed above the pixel electrodes and converting incident light into electric signals; a transparent electrode formed on the photoelectric converting film; charge accumulating regions of an n-type each (i) formed in the epilayer to correspond to one of the pixel electrodes, (ii) electrically connected to the one corresponding pixel electrode, and (iii) accumulating signal charges generated by the photoelectric converting film through the photo-electrically conversion; charge barrier regions of a p-type each formed in the epilayer to contact a bottom of a corresponding one of the charge accumulating regions; and charge draining regions of an n-type each formed in the epilayer to contact a bottom of a corresponding one of the charge barrier regions.

Growing community of inventors

Osaka, Japan

Yusuke Sakata