Hitachi, Ltd.

Renesas Technology Corp.

Yusuke Nitta

Toshihiro Hattori

A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

Growing community of inventors

Tokyo, Japan

Yusuke Nitta