Nec Corporation

Tohoku University

Yonex Kabushiki Kaisha

Yusuke Matsushima

Takumi Sakaguchi

Yasufumi Konishi

An artificial shuttlecock feather for implanting in a circular ring shape into a shuttlecock base, including: a vane section and a rachis section having one end in an axial direction of the rachis section fixed to the base and supporting the vane section provided to another end side of the rachis section, a hole being formed in the vane section so as to penetrate the vane section, and a porosity of a first region of the vane section being lower than a porosity of a second region of the vane section, the first region spanning from an edge on the one end side in the axial direction to a predetermined position further toward the one end side than a center of vane section in the axial direction, the second region spanning from the predetermined position to an edge on the other end side in the axial direction.

Artificial shuttlecock feather and shuttlecock

In an exemplary aspect of the invention, a clock signal amplifier circuit includes an amplifier circuit, a first switch part, and a second switch part. The amplifier circuit amplifies a clock signal. The first switch part controls ON/OFF of the amplifier circuit according to a select signal. The second switch part opens and closes complementarily to the first switch part according to the select signal. The amplifier circuit receives a test clock signal used in a test mode operation state through the second switch part. Further, the amplifier circuit outputs a signal generated by amplifying an input signal serving as the clock signal, or the test clock signal, according to the select signal.

Clock signal amplification circuit, control method thereof, and clock signal distribution circuit

A signal level adjustment system adjusting a level of signal outputted from a signal output circuit is realized. An input buffer threshold adjustment unit sets a threshold of a signal input circuit to a first variable value. A signal level adjustment unit adjusts an output level of a first signal at the signal output circuit until a voltage of the first signal outputted from the signal output circuit and inputted to the signal input circuit falls into a given range determined based on the threshold.

Signal level adjustment method, signal level adjustment system and signal level adjustment circuit

An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.

Output level stabilization circuit and CML circuit using the same

An analog-differential-circuit test device includes transfer gatesandfor isolating in the test mode an input pair of an analog differential circuit from input nodes IN and INB, a voltage adjusting circuit for generating a voltage pair controlled by a control signal fed from outside of the LSI and input to the input pair during the test mode, and a flip-flop for latching an output from the analog differential circuit. A High-output input characteristic and a Low-output input characteristic of the analog differential circuit itself are measured in the LSI.

Analog-differential-circuit test device

A master-slave-type scanning flip-flop circuit is capable of operating at a higher speed by reducing a load capacity of a clock controller. The master-slave-type scanning flip-flop circuit is used to test a semiconductor integrated circuit device, and has a master latch and a slave latch each for temporarily holding an input signal, a first scan controller, a clock controller, and a second scan controller. The first scan controller receives an output signal from the master latch and outputs the received output signal in synchronism with a scan clock which is a clock for testing the semiconductor integrated circuit device, when the semiconductor integrated circuit device is tested. The clock controller receives an output signal from the first scan controller and outputs the received output signal to the slave unit in synchronism with a predetermined clock when in a normal mode of operation. The second scan controller has an input terminal connected to an output terminal of the first scan controller, and outputs a scan-out signal corresponding to a scan-in signal which is an input signal for testing the semiconductor integrated circuit device, in synchronism with the scan clock when the semiconductor integrated circuit device is tested.

Growing community of inventors

Tokyo, Japan

Yusuke Matsushima