Mitsubishi Electric Corporation

Renesas Technology Corp.

Yusuke Kawase

Tadaharu Minato

Kazunori Kanada

Junichi Yamashita

Manabu Yoshino

Takeshi Kishida

Takuichiro Shitomi

A method for manufacturing a semiconductor device includes the steps of forming a layer of a second conductivity type on a top-surface side of a substrate of a first conductivity type, and forming a buffer layer by performing a plurality of ion implantation steps, each of the ion implantation steps implanting ions of an impurity of the first conductivity type into a bottom-surface side of the substrate with an ion implantation angle with respect to a bottom surface of the substrate fixed, the ion implantation angle of a subsequent one of the ion implantation steps being smaller than that of the previous ion implantation step, wherein in the buffer layer formation step, the plurality of ion implantation steps is performed at a fixed acceleration energy.

Method for manufacturing semiconductor device having buffer layer

A laser annealing device of the present invention includes a stage on which a heating object is placed, a first laser element which emits first continuous laser light, a first optical system which leads the first continuous laser light to the heating object to form a first application region on the heating object, a second laser element which emits second continuous laser light having a wavelength shorter than that of the first continuous laser light, a second optical system which leads the second continuous laser light to the heating object to form a second application region on the heating object, and a system controller which executes scanning with the first application region and the second application region so that each portion of the heating object is scanned with at least part of the first application region before being scanned with the second application region.

Laser annealing device with multiple lasers

According to the present invention, since the buffer layer is formed by multiple ion implantations of different acceleration energies and the non-diffusion region in which impurity do not diffuse is left between the buffer layer and the collector layer, the semiconductor device which can supply sufficient holes to the drift layer at the turn-off can be manufactured while the withstand voltage is ensured.

Semiconductor device manufacturing method

A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.

Method of manufacturing semiconductor device

On a silicon oxide film including the interior of an opening a semispherical RGP film is deposited. At a temperature lower than that allowing a crystal of silicon to be grown a BPTEOS film is deposited to fill the opening. Then a portion other than the semispherical RGP film introduced in the opening is chemically mechanically polished and thus removed. This contributes to reduced crystal growth of silicon at the semispherical RGP film and hence reduced scattering and/or removal of the RGP film for example when a CMP step is performed. Subsequently the semispherical RGP film is annealed to grow a crystal of silicon to form a generally spherical RGP film. Thus a storage node can have an increased surface area and a capacitor can have increased capacity.

Method of fabricating semiconductor device

Provided is a semiconductor device manufacturing method in which the numbers of photolithography and anisotropic dry etching processes are reduced to simplify the manufacturing steps; and it is avoided that the presence of an etching stopper film complicates the manufacturing steps in a region where no capacitor is formed, and also causes malfunction in a contact plug. Specifically, an anisotropic dry etching using a resist mask (RM ) is performed to form an opening (OP ) extending through at least an interlayer insulating film ( ). Even after an etching stopper film ( ) is exposed to the bottom part of the opening (OP ), the anisotropic dry etching is continued, using the etching stopper film ( ) as etching mask, in order to form a contact hole (CH ) extending through an interlayer insulating film ( ) to source/drain regions ( ). Therefore, the opening (OP ) and contact hole (CH ) are obtainable at a time in the same etching step.

Growing community of inventors

Tokyo, Japan

Yusuke Kawase