Fujitsu Corporation

Fujitsu Frontech Limited

Fijitsu Limited

Yusuke Kawasaki

Shigeru Hashimoto

Koken Yamamoto

Yoshiyasu Sugimura

Ryoichi Yanagi

Hiroshi Sakurai

Tomomi Shiobara

Yoshinori Tanaka

Manabu Kai

Takashi Yamagajo

Masahiko Shimizu

Teruhisa Ninomiya

Yuji Seki

Osamu Kuroda

Shimpei Komatsu

A tag access apparatus accesses an RFID tag provided with a first antenna having a radio wave directivity along a longitudinal direction of a plurality of test tubes arranged at a predetermined interval. The tag access apparatus has a multi-filler helical antenna which is provided in a direction opposite to the radio wave directivity of the first antenna and which maintains an electric field strength at a central part of the multi-filler helical antenna at a level that allows access to the RFID tag, at the time of access to the RFID tag.

Tag access apparatus

A planar antenna includes: first and second conductors each of which forms a microstrip line in combination with a ground electrode, and which are arranged in parallel with each other on a substrate; a plurality of first resonators disposed between the first conductor and the second conductor which electromagnetically couple the first conductor at one longitudinal end of each of the first resonators to generate electric fields which are in phase with each other; and at least one second resonator disposed between the first conductor and the second conductor which electromagnetically couples the second conductor at one longitudinal end of the at least one second resonator to generate an electric field which is in phase with the electric fields generated by the plurality of first resonators, wherein the at least one second resonator is arranged alternately with the plurality of first resonators.

Planar antenna

A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, internal devices and a bus line connecting the CPU to the internal devices and extending externally, and the external circuit including external devices provided externally of an externally extending portion of the bus line. The internal circuit further including a ciphering sectionprovided at an entrance to an external side and ciphering addresses and data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.

Processing apparatus and integrated circuit to prevent illicit access and reverse engineering

An RFID transceiver device is capable of high sensitivity reception, by the reduction of noise, irrespective of the distance to the tag. The RFID transceiver device includes a delay circuit between a local oscillation circuit and a demodulation circuit, wherein the amount of delay of the delay circuit is set to a magnitude corresponding to the path difference between the path of leakage, via a duplexer into the demodulation circuit, of transmission signal output from the local oscillation circuit for transmission, and the path of direct input of the local oscillation signal from the local oscillation circuit to the demodulation circuit.

RFID transceiver device

An information processing apparatus includes a process part implementing an access to a designated address having an access level, an access detector detecting the access, and an access part being capable of changing the access level of the designated address when the access is detected by the access detector.

Information processing apparatus and method of controlling an access level

Authentication circuits are provided between a debug I/F circuit and a debug terminal. The authentication circuit transmits a transmission key externally at the time of activation, and authenticates based on a reception signal and the transmission key, and enables access to the debug I/F. Thus, it is possible to prevent a spurious access from the debug I/F by a third person by the authentication circuit.

IC, IC-mounted electronic device, debugging method and IC debugger

An access violation of the program is monitored by the access monitor which is a hardware. The access monitor acquires a signal input from the CPU to a memory. The access monitor includes an access permission table as information of the memory region to be permitted to each program, and detects the access violation of the signal from the CPU by referring thereto. In this manner, the unjust access is monitored by the hardware, thereby preventing the unjust access by rewriting in software.

Access monitor and access monitoring method for monitoring access between programs

An encryption processor for encrypting and decrypting data that ensures data security by preventing illegal deciphering or leakage of the data. The encryption processor includes a CPU for running a program, a ROM for storing the program run by the CPU, a RAM used as a work area while the CPU is running the program, an I/O section for sending/receiving data to/from an external device, and an encryption section for decrypting encrypted data and encrypting plain text data.

Secure encryption processor with tamper protection

A protocol control integrated circuit configured by integrating, on one chip, hardware and control programs necessary for conducting data interchange through communications with portable type mediums, and used in common among various types of apparatus. Thus, the integrated circuit is constructed by integrating, on one chip, a storage section for storing a control program prepared for protocols for a plurality of digital money different in mode from each other, a processing section for controlling the handling of the plurality of digital money, different in mode, by running the control program stored in the storage section, and an interface circuit connected to an external circuit including at least one of an external processing section and an external storage section for fulfilling an interface function between the external circuit and the processing section. Further this invention is applicable to various types of transaction apparatus capable of handling, for example, digital money and credit transactions.

Integrated circuit for protocol control

The installation method makes possible the installation of new programs, while maintaining security, in a system LSI device. The installation method comprises a step for receiving the signature dataof a program, a step for checking for interference with other already installed programs on the basis of said signature data, and a step for authorizing the installation of programs with which there is no interference. A declaration of signature data is elicited from a program being installed; a check for interference among programs is performed based on this, authentication is performed, and the installation of interfering programs is prevented or the installation of programs with which there is no interference is executed. It therefore becomes possible to install new programs while protecting high-security programs.

Program installation method, program installation system, program executing apparatus, and storage medium

A proximity IC card (PICC) which relates to and provides a carrier synchronization type demodulator, which is able to stably receive a PSK signal from a PICC and is enhanced in noise immunity, and which is realized at a low cost and in such a way as to have a small size. The carrier synchronization type demodulator is adapted to receive and demodulate PSK-modulated subcarrier signals to be synchronized with and superposed onto a sent carrier signal. This demodulator includes a carrier detecting device for detecting the subcarrier signals successively received in a predetermined time, a phase-change-point detecting device for detecting a phase change point of the subcarrier signal after the subcarrier signal is detected, and a data reception control device for controlling the reception of data of a predetermined format by employing a moment, at which the phase change point is detected, as a synchronization start point for receiving data, and by using an internal clock that is synchronized with the sent carrier signal by using the moment as a starting point of synchronization.

Carrier synchronization type demodulator for PSK signal

The present invention relates to a device connection state recognizing method capable of recognizing a connection state of devices without addition of signal lines dedicated to detection. Thus, in the method according to this invention, a portion of or all of a plurality of data signal lines are connected through pull-up resistors to a high electric potential or connected through pull-down resistors to a low electric potential in accordance with the connection state of the devices, and a processing unit reads, as structure information data, a high electric potential state/low electric potential state generated by the pull-up resistor/pull-down resistor in the portion of or all the plurality of data signal lines to recognize the connection state of the devices on the basis of the read structure information data. This invention is applicable to a various types of processing units which are to be connected through a common data bus to a plurality of devices.

System for recognizing of a device connection state by reading structure information data which produced by pull-up resistor and pull-down resistor

The present invention relates to a proximity IC card (PICC). More particularly, the present invention relates to and provides a detection circuit of a simple structure, which is easy to set up in a PICC and a proximity coupling device (PCD) for transmitting data to and receiving data from the PICC. This detection circuit is operative to detect a subcarrier signal sent from a PICC and superposed onto a carrier signal received through an antenna. Further, this detection circuit comprises a bias circuit for applying predetermined DC potential to a signal received from the antenna, a rectifier circuit for extracting a subcarrier signal superposed onto the carrier signal by rectifying a signal received from the antenna at a bias point, and an amplifier circuit for amplifying the subcarrier signal extracted at the bias point.

Detection circuit for proximity IC card device

A numerical data processing apparatus has: at least three loading apertures onto each of which a storage medium is loaded, said storage medium storing numerical data standing for a numerical value to be converted into an amount of money and having an equivalent value to a value of currency of the amount of money corresponding; a transfer path network connected to all of said at least three loading apertures for transferring the numerical data among the storage media loaded onto said at least three loading apertures; and a transfer control unit for providing such a control that a transfer source and a transfer destination of a data transfer by said transfer path network are identified, an amount of money is obtained in accordance with an operation, and numerical data of the obtained amount of money corresponding is transferred from the transfer source to the transfer destination.

Numerical data processing apparatus and numerical data processing method

In a system having an internal memory storing internal contents wherein an external memory for storing external contents is detachably mounted on said processing apparatus, for performing a processing according to the internal contents stored in said internal memory and the external contents stored in said external memory, a contents check method decides validity of the external contents stored in said external memory. The external contents stored in said external memory involve original check result information representative of a check result associated with validity of the external contents and original check result position information representative of a storage position of the original check result information. The external contents stored in said external memory is checked in accordance with a predetermined check algorithm to obtain a check result. The check result obtained is compared with a check result represented by the original check result information stored in a storage position indicated by the original check result position information to decide validity of the external contents stored in said external memory.

Growing community of inventors

Kawasaki, Japan

Yusuke Kawasaki