Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Other

Yusuke Kanno

Hiroyuki Mizuno

Takao Watanabe

Nobuhiro Oodaira

Kazumasa Yanagisawa

Yoshihiko Yasu

Takeshi Sakata

Kenji Hirose

Takahiro Irita

Seiji Miura

Kazushige Ayukawa

Jun Satoh

Tadanobu Toba

Naohiko Irie

Kazuo Otsuga

Kenichi Osada

Tetsuya Yamada

Makoto Saen

Kiyoo Itoh

Nobuyasu Kanekawa

Masahiro Shiraishi

Masafumi Onouchi

Takumi Uezono

Hideo Harada

Koichiro Ishibashi

Satoshi Nishikawa

Masanao Yamaoka

Kazuo Tanaka

Kotaro Shimamura

Goichi Ono

Shigenobu Komatsu

Shunsuke Toyoshima

Takeo Toba

Toru Motoya

Kenichi Yoshizumi

Yohihiko Yasu

Keisuke Yamamoto

Hiromichi Yamada

Masayuki Miyazaki

Tsutomu Yamada

Satoru Akiyama

Yasuhisa Shimazaki

Teppei Hirotsu

Akira Kotabe

Ryuta Tsuchiya

Kenichi Shimbo

Takashi Kuraishi

Satoshi Misaka

Yoshio Takazawa

Toshinobu Shinbo

Masashi Ohkawa

Satoru Akasaka

Gou Shinkai

A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

Application logic, and verification method and configuration method thereof

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Semiconductor integrated circuit device

The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside. This improves safety and reliability when severe safety criteria are required such as in a case of monitor-display in industrial plant equipment.

Display device

Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

Semiconductor LSI design device and design method

The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.

Programmable device, error storage system, and electronic system device

Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STEto STEwhich are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE) of the plurality of storage elements STEto STEincludes a majority decision unit (for example,) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.

Semiconductor device

An object of the present invention is to provide a high reliable/high safe programmable logic device with high error resistance. The present invention provides a programmable logic device that has a plurality of configuration memories. The configuration memories are divided into a plurality of areas and are arranged and a part of the plurality of areas is set to a high reliable area where reliability of the configuration memory is higher than in the other area.

Programmable logic device and logic integration tool

In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.

Programmable circuit device and configuration information restoration method

Semiconductor integrated circuit device with independent power domains

A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.

A semiconductor integrated circuit device provided with a first circuit block BLK, a second circuit block DRVand a conversion circuit MIOfor connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIOto MIO) are commonly used for connecting circuit blocks.

Growing community of inventors

Kodaira, Japan

Yusuke Kanno