Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Device Engineering Co., Ltd.

Yusuke Jyouno

Takayuki Kawahara

Katsutaka Kimura

Naoki Miyamoto

Syunichi Saeki

To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Nonvolatile semiconductor memory device which stores multi-value information

Nonvolatile semiconductor memory device having plural memory cells which store multi-value information

Nonvolatile semiconductor memory device for storing multivalue

The memory mat is divided in two banks, which share the sense & latch circuit. As an example of the circuit operation, the information contained in the memory cells in a block of four bit lines BL11a-BL14a connected to a word line WL1a in the memory array MAa of the bank A is temporarily stored in the sense & latch circuits SL11-SL14. The information of bit lines is latched to the sense & latch circuit SLa through the sub-input/output signal lines IO1a and IO2a by the switches YS1a and YS2a that alternately operates at a cycle two times that of the external clock. The latched information is then output onto the input/output signal line IOa by the switch SWa in synchronism with the clock. After the four bit lines BL11a-SB14a have been read out, the sense & latch circuits SL11-S114 in that block are reset and the bit lines on the bank B are precharged while the information on the bank A is being output. After the reading on the bank A is finished, the word line on the bank B is raised to a high level to execute the read operation in the similar manner. In this way, the word lines on the two banks are alternately raised to the high level for continuous and alternate reading. This configuration provides a nonvolatile semiconductor memory device which allows high-speed block reading.

Nonvolatile semiconductor memory device

Nonvolatile semiconductor memory device which stores multi-value

This invention provides a nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing the word line, and a plurality of memory cells including MOS transistors. Each of control gates of the MOS transistors are coupled to the word line and each of drains thereof are coupled to the bit lines, respectively. Each of the MOS transistors also has a floating gate. Further, the non-volatile semiconductor memory device comprises latch circuits, first switches, a sense amplifier coupled to the plurality of bit lines in common, and second switches. The latch circuits are coupled to the plurality of bit lines through the first switches which are coupled between the plurality of bit lines and the latch circuits, respectively. The second switches are respectively coupled between the plurality of bit lines and the sense amplifier, thereby coupling the sense amplifier to the bit lines. Each of the plurality of first switches includes a MOS transistor whose source-drain path is between a corresponding one of the plurality of bit lines and a corresponding one of the latch circuits, respectively. When data is to be read from a memory cell selected out of the plurality of memory cells, the plurality of first switches are turned off and one of the second switches between the selected memory cell and the sense amplifier is turned on.

Growing community of inventors

Higashimurayama, Japan

Yusuke Jyouno