Sandisk Technologies Inc.

Yusuke Ikawa

Kiyohiko Sakakibara

Masaaki Higashitani

Eisuke Takii

Tsuyoshi Sendoda

Kei Samura

Raghuveer S Makala

Hiroyuki Ogawa

Yanli Zhang

Rahul Sharangpani

Fei Zhou

Senaka Kanakamedala

Masanori Tsutsumi

Seiji Shimabukuro

Yoshitaka Otsu

Somesh Peri

Koichi Ito

Kengo Kajiwara

Akira Matsudaira

Keerti Shukla

Takeshi Kawamura

Naoto Hojo

Cheng-Chung Chu

Yoshinobu Tanaka

Kei Nozawa

Ryoichi Ehara

Yashushi Doda

Zhiwei Chen

Nagarjuna Asam

Seyyed Ehsan Esfahani Rashidi

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

Modelling and prediction of virtual inline quality control in the production of memory devices

Virtual quality control interpolation and process feedback in the production of memory devices

Virtual metrology for feature profile prediction in the production of memory devices

A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.

Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same

Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.

Three-dimensional junction memory device and method reading thereof using hole current detection

A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof

Threshold voltage shift due to programming of a neighboring memory element can be reduced or suppressed by forming a compositionally modulated charge storage layer in a three-dimensional memory device. The compositionally modulated charge storage layer can be formed by providing an oxygen-containing dielectric silicon compound layer outside a tunneling dielectric layer, and subsequently nitriding portions of the oxygen-containing dielectric silicon compound layer only at levels of the control gate electrodes. An alternating stack of sacrificial material layers and insulating layers can be employed to form a memory stack structure therethrough. After removal of the sacrificial material layers, a nitridation process can be performed to convert physically exposed portions of the oxygen-containing dielectric silicon compound layer into silicon nitride portions, which are vertically spaced from one another by remaining oxygen-containing dielectric silicon compound portions that have inferior charge trapping property to the silicon nitride portions.

Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures

Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding. Reduction in corner rounding can increase effectiveness of the control gates for a three-dimensional memory device.

Method of reducing control gate electrode curvature in three-dimensional memory devices

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Yokkaichi, Japan

Yusuke Ikawa