Hitachi, Ltd.

Yusuke Fukumura

Yutaka Uematsu

Satoru Watanabe

Takayuki Ono

Hideki Osaka

Nobukazu Kondo

Yoshihiro Kondo

Hitoshi Ueno

Akio Idei

Masabumi Shibata

Satoshi Muraoka

Yuichi Fukuda

Kazunori Nakajima

Michinori Naito

Patrick Hamilton

Takashi Miyagawa

Hiroshi Kakita

Taishi Sumikura

Masaya Nakahata

Takashi Oomori

A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein

A computer comprising: a processor; a memory; and an I/O device, the memory including at least one first memory element and at least one second memory element, wherein a memory area provided by the at least one second memory element includes a data storage area and a data compression area, wherein the computer comprises a virtualization management unit, and wherein the virtualization management unit is configured to: set a working set for storing data required for processing performed by a virtual machine in generating the virtual machine, and control data stored in the working set in such a manner that part of the data stored in the working set is stored in the data compression area based on a state of accesses to the data stored in the working set.

Computer and memory management method

The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, which reduces the mantissas from three to two terms, which carries out addition on the mantissas of the two terms, a normalization circuit which makes left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.

Three-term input floating-point adder-subtractor

Growing community of inventors

Tokyo, Japan

Yusuke Fukumura