Mitsubishi Electric Corporation

Yusuke Fukada

Atsushi Narazaki

Kazuya Konishi

Ryu Kamibaba

Kenji Suzuki

Katsumi Nakamura

Masayoshi Tarutani

Mariko Umeyama

Included are a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate, a source layer of a first conductivity type formed on the semiconductor substrate, a base layer of a second conductivity type formed on the semiconductor substrate, a collector electrode formed under the semiconductor substrate, a plurality of active trench gates formed on a top-surface side of the semiconductor substrate and connected to the gate electrode, and a plurality of dummy trench gates formed on the top-surface side of the semiconductor substrate and not connected to the gate electrode. First structures, each including three or more of the active trench gates arranged side by side, and second structures, each including three or more of the dummy trench gates arranged side by side, are alternately provided.

Semiconductor device

A semiconductor device includes a first semiconductor layer on one main surface of a semiconductor substrate; a plurality of trench gates in the first semiconductor layer extending to reach the inside of the semiconductor substrate; a second semiconductor layer selectively provided in an upper portion of the first semiconductor layer between the trench gates; an isolation layer in contact with a side surface of the second semiconductor layer and extends in the first semiconductor; and a third semiconductor layer in the upper portion of the first semiconductor layer between the trench gates and has at least one side surface in contact with the trench gate. The isolation layer is between and separates the second semiconductor layer and the third semiconductor layer from each other and is formed to extend to the same depth as, or to a position deeper than the second semiconductor layer.

Semiconductor device and method for manufacturing the same

A p-type base layer () is formed on a surface of an n-type silicon substrate (). First and second n-type buffer layers ()are formed on a back surface of the n-type silicon substrate (). The first n-type buffer layer () is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (). The second n-type buffer layer () is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate () than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

Semiconductor device and method of manufacturing the same

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Tokyo, Japan

Yusuke Fukada