Thine Electronics, Inc.

Hitachi, Ltd.

Johns Hopkins University

The University of Tokyo

Yusuke Fujita

Satoshi Miura

Shunichi Kubo

Naoyuki Kanda

Tetsuya Iizuka

Yoshihiko Nakamura

Ryota Kamoshida

Katsu Yamane

Kenji Nagamatsu

Yoshinobu Oshima

Yuji Gendai

Ryu Takeda

Shota Horiguchi

Daigo Takahashi

Shinji Watanabe

Norihiko Nakasato

Akihiko Murai

A communication device includes a controller, a differential input termination resistor, a linear laser driver, transmitted signal detector, a linear transimpedance amplifier, a linear variable gain amplifier, a linear output driver, a pulse counter, a received signal detector, and an amplitude detector. The controller outputs a Term signal for setting a resistance value of the differential input termination resistor, a TxEN signal and an LS signal for controlling an operation of the linear laser driver, an RxEN signal for controlling operations of the linear TIA, the linear VGA, and the linear output driver, and a GCTL signal for controlling a gain of the linear VGA.

Communication device, terminal device and active optical cable

An audio analysis platform may receive a portion of an audio input, wherein the audio input corresponds to audio associated with a plurality of speakers. The audio analysis platform may process, using a neural network, the portion of the audio input to determine voice activity of the plurality of speakers during the portion of the audio input, wherein the neural network is trained using reference audio data and reference diarization data corresponding to the reference audio data. The audio analysis platform may determine, based on the neural network being used to process the portion of the audio input, a diarization output associated with the portion of the audio input, wherein the diarization output indicates individual voice activity of the plurality of speakers. The audio analysis platform may provide the diarization output to indicate the individual voice activity of the plurality of speakers during the portion of the audio input.

Multi-speaker diarization of audio input using a neural network

The communication deviceincluded in the active cable comprises a controller, a comparator, a resistor, a voltage source, and a redriver. The comparatorreceives the voltage value of the SBU signal line and the reference voltage value output from the voltage source, and compares the voltage value of the SBU signal line with the reference voltage value to detect the level of the sideband signal. The controllerreceives the detection result of the sideband signal level from the comparator, and sets the redriver, which is an active device, to the low-power-consumption state when the sideband signal level stays at L level for a predetermined period of time or longer.

Communication device and active cable

An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.

Crosstalk cancellation circuit, transmitter, and transmission and reception system

A multi-lane serializer deviceincludes serializer circuitstoand a controller. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controllerwhen the detected phase difference is abnormal. When the controllerreceives the abnormal detection signal from any of the serializer circuits, the controllertransmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.

Multi-lane serializer device

A transmitting and receiving device includes a controller, a driver, a specific pattern generator, a transmitting signal detector, an amplifier, a differential amplifier, an average current detector, and a received signal detector. In a non-signal period, the controller causes a current signal to be input from the driver to a laser diode and causes an optical signal to be output from the laser diode. When an optical signal of a specific pattern output from the other-side laser diode reaches a photodiode over a period of length that depends on an average value of a current signal output from the other-side photodiode that receives the optical signal, the controller adjusts a magnitude of the current signal input from the driver to the laser diode based on the length of the period of the optical signal of the specific pattern.

Transmitting and receiving device, terminal device, and transmitting and receiving system

A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

PLL circuit

A transmission/reception systemincludes a transmission deviceand a reception devicethat is connected to each other through differential signal linesand a signal line, and receives a differential signal that is sent out from the transmission deviceusing the reception device. The transmission deviceincludes a signal output unit, a request input unit, and a resistor. The signal output unitsends out a differential signal from a pair of output terminals Pand Pthat are connected to the differential signal lines. A common voltage of each of the pair of output terminals Pand Pis constant over a state where no electric power is supplied and an idle state.

Transmission device and transmission/reception system

A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer Boutputs an m-th input signal when the signal levels of both an m-th control signal Cand an n-th control signal Cof M control signals are significant, and the m-th pre-stage buffer Benters into a high-impedance state when the signal level of at least one of the m-th control signal Cand the n-th control signal Cis non-significant. The output buffer Bsequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.

Signal-multiplexing device

This embodiment relates to a transmitter that has a structure to suppress an increase in device occupancy area on a semiconductor substrate. The transmitter includes an output driver, a duplication driver, a reference voltage generation unit, a first selection unit, a second selection unit, a comparison unit, and a control unit. The first selection unit selects a first or second test voltage outputted from a duplication driver in which a resistance value is set in cooperation with the output driver. The second selection unit selects a first or second reference voltage outputted from the reference voltage generation unit. The comparison unit compares magnitudes of the first test voltage and the first reference voltage during a first operation period and compares magnitudes of the second test voltage and the second reference voltage during a second operation period different from the first operation period.

Transmitter and transmission/reception system including the same

A PLL circuit of one embodiment has a structure for preferably setting the FV characteristic of an LC-VCO. The PLL circuit includes a voltage controlled oscillator, a phase comparator, a charge pump, a loop filter, and an FV characteristic adjustment unit setting the FV characteristic. The voltage controlled oscillator has an FV characteristic indicating the relationship between a control signal and a frequency and outputs an oscillation signal having a frequency corresponding to the control signal based on the FV characteristic. The phase comparator detects a phase difference between an input signal and the control signal. The charge pump outputs a corrected voltage value changed according to the phase difference. The loop filter outputs a control voltage value changed in response to corrected voltage value variations. The FV characteristic adjustment unit generates an FV characteristic control signal by a mean corrected voltage value.

The signal multiplexerinputs two selection signals CLK&#x3c;&#x3e;, CLK&#x3c;&#x3e; that sequentially reach significant levels, inputs two input signals IN&#x3c;&#x3e;, IN&#x3c;&#x3e;, and outputs, from an output terminal, a signal OUT that depends on an m-th input signal IN&#x3c;m&#x3e; of the two input signals when an m-th selection signal CLK&#x3c;m&#x3e; of the two selection signals is at the significant level. The signal multiplexerincludes a resistance unitand two drive units. Each of the drive unitsincludes a driving switch, a selecting switch, and a potential stabilizing switch. When one of the selecting switchand the potential stabilizing switchin each of the drive unitsis in a closed state, the other is in an open state.

Signal multiplexer

A duty compensation device of one embodiment has a structure capable of more accurately setting a duty of a clock within an appropriate range. The duty compensation device comprises a duty adjusting unit, a duty measuring unit, a controlling unit. The duty measuring unit generates a sampling clock of a frequency fthat is asynchronous to the clock over an n-th period T(n=1 to N and N is an integer of 3 or more), and obtains measurement information for specifying the duty of the clock by using the sampling clock. The controlling unit determines a control code to be given to the duty adjusting unit based on control code candidates obtained for each of the N periods Tto Tand the control code candidates in which the duty specified by measurement information obtained by the duty measuring unit is within a predetermined range.

Duty compensation device

Provided is a voice search technology that can efficiently find and check a problematic call. To this end, a voice search system of the present invention includes a call search database that stores, for each of a reception channel and a transmission channel of each of a plurality of pieces of recorded call voice data, voice section sequences in association with predetermined keywords and time information. The call search database is searched based on an input search keyword, so that a voice section sequence that contains the search keyword is obtained. More specifically, the voice search system obtains, as a keyword search result, a voice section sequence that contains the search keyword and the appearance time thereof from the plurality of pieces of recorded call voice data, and obtains, based on the appearance time in the keyword search result, the start time of a voice section sequence of another channel immediately before the voice section sequence obtained as the keyword search result, and thus determines the start time as the playback start position for playing back the recorded voice. Then, the playback start position is output as a voice search result.

Voice search system, voice search method, and computer-readable storage medium

A serializer device () includes a first latch unit (), a second latch unit (), a conversion unit (), a frequency division unit (), a load signal generation unit (), a phase difference detection unit (), and a reset instruction unit (), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit () detects a phase difference between a first clock (CLK) applied to the first latch unit () and a third clock (CLK) applied to the second latch unit (). The reset instruction unit () outputs a reset instruction signal (RSTn) to the frequency division unit () when the phase difference is not within a target range.

Growing community of inventors

Tokyo, Japan

Yusuke Fujita