Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Yusuke Arayashiki

Kikuko Sugimae

Yosuke Murakami

Kazuhiko Yamamoto

Takayuki Ishikawa

Hidenori Miyagawa

Kensuke Takahashi

Tomohito Kawashima

Yusuke Kobayashi

Nobuyuki Momo

Kana Hirayama

Noboru Shibata

Reika Ichihara

Kazuaki Nakajima

Shosuke Fujii

Katsuya Nishiyama

Akira Takashima

Daisuke Matsushita

Takeshi Ishizaki

Satoshi Nagashima

Yoshifumi Nishi

Akira Hokazono

Kouji Matsuo

Akiyuki Murayama

Hideki Inokuma

Yefei Han

Takashi Haimoto

Masanobu Baba

Kyosuke Sano

Motohiko Fujimatsu

Takahiro Nonaka

According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2second distributions are separately formed two by two. The circuit then sets 2third distributions for the 2sections.

Semiconductor memory device and method

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

Resistive random access memory device with three-dimensional cross-point structure and method of operating the same

A semiconductor storage device includes a third semiconductor layer and a fourth semiconductor layer. The third semiconductor layer has a first width; the third semiconductor layer and a first insulating layer are disposed apart with a first distance; the third semiconductor layer and a second insulating layer are disposed apart with a second distance; the fourth semiconductor layer has a second width; the fourth semiconductor layer and the first insulating layer are disposed apart with a third distance; and the fourth semiconductor layer and the second insulating layer are disposed apart with a fourth distance. A shorter one of the first distance and the second distance is shorter than a shorter one of the third distance and the fourth distance, and the first width is larger than the second width.

Semiconductor storage device

According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material.

Resistive random access memory device and method for manufacturing the same

A semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring.

A semiconductor memory device includes a semiconductor pillar including a semiconductor layer and extending along a first direction, a first wiring extending along a second direction crossing the first direction, a first electrode between the semiconductor pillar and the first wiring, a first insulating layer between the first electrode and the first wiring and adjacent to the first electrode, a second insulating layer between the first insulating layer and the first wiring and adjacent to the first insulating layer, the second insulating layer having a higher dielectric constant than the first insulating layer, and a third insulating layer between the second insulating layer and the first wiring. A shortest distance between the second insulating layer and the semiconductor layer in the second direction is greater than a shortest distance between the first electrode and the semiconductor layer in the second direction.

Stacked body semiconductor storage device having an electrode between a pillar and a wiring and insulating layers having different dielectric constants between the electrode and the wiring

According to one embodiment, a semiconductor memory device includes a substrate, a first signal line, a first conductive layer, a first storage layer and a first insulation layer. The first signal line extends in a first direction crossing the substrate. The first conductive layer extends in a second direction crossing the first direction and being parallel to the substrate, and has a first surface and a second surface that is away from the first signal line in a third direction crossing the first and second directions. The first storage layer is provided between the first signal line and the first conductive layer. The first insulation layer is provided between the second surface and the first storage layer.

Semiconductor memory device

A storage device includes: a substrate; a first conductive layer extending in a first direction; a second conductive layer adjacent to the first conductive layer in a second direction, and extending in the first direction; a third conductive layer extending in a third direction; a fourth conductive layer extending in the second direction; a fifth conductive layer disposed on the second conductive layer, extending in the third direction, and being electrically connected to the fourth conductive layer; a first storage layer disposed between the third conductive layer and the fourth conductive layer; a first semiconductor layer disposed between the first conductive layer and the third conductive layer; a second semiconductor layer disposed between the second conductive layer and the fifth conductive layer; and a first gate electrode extending in the second direction and being shared by side surfaces of the first semiconductor layer and the second semiconductor layer.

Storage device

A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.

A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.

Storage device having variable resistance layer

According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.

Memory device

A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer provided between the first and second conductive layers. The variable resistance layer includes a first layer having a semiconductor or a first metal oxide containing a first metal, and a second layer provided between the first layer and the second conductive layer, having a second metal oxide containing a second metal, and having crystal grains that are not in contact with at least one of an end face of the second layer on a side of the first conductive layer or an end face of the second layer on a side of the second conductive layer.

Growing community of inventors

Kanagawa-ken, Japan

Yusuke Arayashiki