Asahi Kasei Emd Corporation

Yusuke Aiba

The present invention provides a continuous-time delta-sigma modulator which is configured with an SC (SCR) feedback DA () for improving tolerance to jitter for a clock signal and operates stably by maintaining a certain feedback amount without being influenced by a change in a production process thereof or an operating temperature condition thereof. By adjusting a reference voltage Vref that determines an output voltage of the SC feedback DA (), it is possible to feed back a certain amount of charge from the SC feedback DA () to a loop filter (). Thereby, operation of the delta-sigma modulator is stabilized.

Delta-sigma modulator

Provided is a transconductance amplifier capable of suppressing variation in the range of a linear relationship between an input voltage and an output current depending on the magnitude of a tuning voltage Vctrl, thereby adjusting transconductance over a wider range of operating input voltages. The transconductance amplifier is configured by a differential pair formed of MOS transistors () having a common source, MOS transistors (), amplifiers (), a voltage generator circuit (), and a differential-pair input voltage generator circuit (). An input differential common voltage Vcm of all differential signals inputted to the differential pair is adjusted so that a difference between Vcm and Vctrl is equal to a constant, in accordance with a change in the tuning voltage Vctrl that controls the transconductance. This enables keeping constant the range in which the transconductance amplifier can achieve good linearity.

Transconductance amplifier

An embodiment of the present invention has a differential pair including a first and second MOS transistors having their sources grounded; a third and fourth transistor with their source terminals connected to drain terminals of the first and second transistors, respectively; a voltage generating circuit for outputting tuning and common voltage so that the ratio between the common and tuning voltage is constant; and a differential pair input voltage generating circuit that receives the input and common voltage to output voltages Vip and Vin to gate terminals of the first and second transistors, respectively. The gate terminal of the fourth transistor is connected to the gate terminal of the third transistor, and the tuning voltage is input to the two terminals.

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Tokyo, Japan

Yusuke Aiba