1. Microsoft Technology Licensing, LLC (9 from 54,638 patents)

2. Qualcomm Incorporated (6 from 41,326 patents)

1. 11803389 - Reach matrix scheduler circuit for scheduling instructions to be executed in a processor

2. 11669333 - Method, apparatus, and system for reducing live readiness calculations in reservation stations

3. 11593117 - Combining load or store instructions

4. 11392410 - Operand pool instruction reservation clustering in a scheduler circuit in a processor

5. 11327763 - Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor

6. 11113068 - Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)

7. 11061677 - Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor

8. 11023243 - Latency-based instruction reservation station clustering in a scheduler circuit in a processor

9. 10956162 - Operand-based reach explicit dataflow processors, and related methods and computer-readable media

10. 10896041 - Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices

11. 10877768 - Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor

12. 10860328 - Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture

13. 10514921 - Fast reuse of physical register names

14. 9304774 - Processor with a coprocessor having early access to not-yet issued instructions

15. 9164772 - Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available