American Microsystems, Inc.

Maxim Integrated Products, Inc.

Yusuf A Haque

Jeffrey A Schuler

Vikram Saletore

Patrick Yin Chan

Roubik Gregorian

Ashraf K Takla

Gideon D Amir

Erwin Ofner

Richard W Blasco

A power level sense circuit which is substantially immune to variations in integrated circuit processing and operating temperature. The sense circuit uses a diode biased to a predetermined average conduction level as the primary element in an envelope detector to detect the envelope of the RF transmit signal. While the DC offset of the diode will vary with temperature and integrated circuit processing, the DC offset is eliminated by an auto zeroing procedure before each power sensing cycle.

Power level sense circuit

A logic signal level translation method and apparatus having very low dropout with respect to the powering rails and having a tri-state mode of operation allowing the output terminal to be driven to voltages beyond the highest supply voltage coupled thereto without significant power dissipation within the circuit. The output circuit includes well or body snatching devices which are controlled to assure that the wells of the output devices are able to follow extremes in voltage of the output terminal without biasing to conduction a PN junction of one or more of the output devices. A preferred embodiment is disclosed.

Logic signal level translation apparatus having very low dropout with

The invention relates to a self-biasing, programmable, universal active filter having an input section which includes an operational amplifier. The amplifier has one output and two input terminals. A first capacitor has one of its terminals coupled to a first of the input terminals of the amplifier and the other terminal serving as an input node to the filter. The second capacitor is coupled between the same input terminal and the output terminal. The filter has a bandpass section having an output and an input coupled to the output terminal of the amplifier. The filter has a low pass section having an output and an input coupled to the output of the bandpass section. The filter has a third capacitor coupled between the first input terminal of the amplifier and the output of the bandpass section. Finally, the filter uses a pair of switched capacitors under clock control, one in parallel with the first capacitor and the other in parallel with the second capacitor, whereby DC current can flow from the input terminal of the filter to first input terminal of the amplifier, and from the same one input terminal of the amplifier to the output terminal of the amplifier during at least a portion of the clock cycle.

Programmable, universal filter with self biasing

A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50%, or any other predefined value.

Frequency doubler with fifty percent duty cycle output signal

A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop. If the output frequency of voltage controlled oscillator is below the predefined frequency range, the limiter circuit provides a high voltage output signal to the control input lead of the VCO in order to pull the input voltage of the voltage controlled oscillator to a voltage which corresponds with the proper operating frequency range of the phase locked loop.

Phase locked loop with high and/or low frequency limit detectors for

A single-shot circuit is fabricated as an integrated circuit except for a single capacitor requiring a single pin to connect to the on-chip circuitry. The single-shot is rendered independent of process variations and operating conditions by incorporating an analog feedback loop. The output of the single shot is detected by an analog circuit which includes a positive and negative voltage generator the ratio of whose voltages is a function of the desired duty cycle. The generators are actuated, respectively, when a pulse exists and when there is no pulse. The analog feedback circuit also includes an integrator for receiving and integrating the positive and negative voltages from the generators. The integrated and amplified voltages are fed back to the last stage of the single-shot circuit. When the duty cycle is high, the voltage that is fed back drives the single shot circuit to reduce the pulse width. When the duty cycle is low, the voltage that is fed back drives the single-shot circuit to increase the pulse width. Thus, the pulse width of the single shot is controlled by the built-in values of the positive and negative voltage generators and is independent of process variations and operating conditions.

Single-shot circuit having process independent duty cycle

A carrier detection circuit includes a rectification stage, an integrator, a comparator, and a digital counter. By utilizing a digital counter, long time constants are provided without the use of external components. If desired, a mark detect circuit is used when a mark must be present to signify the presence of carrier. Hysteresis is provided by the comparator to insure that slight fluctuations in the carrier level do not affect the comparison.

Carrier detection circuit

An operational amplifier has one noninverting input lead (116), and two inverting input leads (117a, 117b). One of these inverting input leads (117a) is utilized to compensate for the effects of the inherent offset voltage (V.sub.off) of the operational amplifier, and the second inverting input lead (117b) receives an input signal to be amplified or compared.

Reference voltage circuit including a three-terminal operational

A differential operational amplifier is provided with a feedback loop which continuously adjusts the common mode voltage level of the amplifier so that it lies in the center of the dynamic range of the amplifier. The feedback loop measures the instantaneous common mode voltage level and compares it with a reference voltage which is set to reflect the desired common mode voltage. An error signal is generated and fed back into the amplifier to adjust the instantaneous common mode voltage level towards the reference level. Frequency compensation is also provided to overcome the phase shift introduced by the use of RC networks.

Differential operational amplifier with common mode feedback

A programmable transversal filter utilizes a plurality of programmable multiplying means. The result of each multiplication is summed by a summing circuit, thus providing an output signal. The delay network comprises a plurality of signal sample and hold circuits which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods. The filter also includes a plurality of reference sample and hold circuits which store error voltages equal to the error voltage component of the voltages provided by the signal sample and hold circuits. A first analog cross-point switch is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means. The filter tap weights remain fixed in the multipliers until reprogrammed, without the need for rotating the tap weights. A second analog cross-point switch is utilized to selectively connect the output voltage from the reference sample and hold circuits to the multiplier means, thereby eliminating the effect of the error voltages on the output voltage of the transversal filter.

Programmable transversal filter

A programmable transversal filter (10) utilizes a plurality of programmable multiplying means (M.sub.1 -M.sub.4). The result of each multiplication is summed by a summing circuit (7), thus providing an output signal (y(t)). The delay network of this invention comprises a plurality of sample and hold circuits (S.sub.1 -S.sub.4) which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods. An analog cross-point switch (51) is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means. By utilizing an analog cross-point switch, a transversal filter having programmable tap weights is constructed wherein the tap weights remain fixed in the multipliers until reprogrammed, without the need for rotating the tap weights among the plurality of multipliers. Furthermore, each input voltage sample is stored in a single sample and hold circuit. Because the transversal filter of this invention does not cycle the tap weights among multipliers, the dynamic range of the output signal of the transversal filter constructed in accordance with this invention is increased over that of prior art programmable transversal filters, with a substantial decrease in fixed pattern noise.

Three-terminal operational amplifier/comparator with offset compensation

An AGC circuit (12) contains a programmable gain stage comprising an operational amplifier (150) and one or more capacitor arrays (101, 121) for controlling the closed loop gain of the operational amplifier. The output signal (V.sub.O) of this operational amplifier is rectified, and the rectified signal is alternately integrated with a reference voltage (V.sub.ref) of opposite polarity to the rectified AGC signal. The polarity of the integrated voltages operates a counter stage (200). The output bits (0.sub.2 -0.sub.N) of the counter are used to control switches (134-2 through 134-N, 135-2 through 135-N, 110-2 through 110-N, 111-2 through 111-N) in the one or more capacitor arrays which control the closed loop gain of the operational amplifier of the AGC circuit of this invention.

Switched capacitor automatic gain control loop

A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (V.sub.error) is inverted and integrated one time for each integration of the input voltage (V.sub.in), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (V.sub.out).

Monolithic programmable gain-integrator stage

A digital to analog converter (100) utilizes a current mirror connected to a reference voltage (V.sub.REF) to generate a constant reference current (I.sub.REF). A voltage divider (R.sub.1 and R.sub.2) is used in conjunction with a plurality of MOS transistors (X.sub.1 -X.sub.N) serving as current mirrors having specific current carrying capabilities which are controlled by selected binary digits (bits) of a digital signal. By the appropriate connection of desired ones of said plurality of MOS transistors, a specific fraction of said reference current is caused to flow through said plurality of MOS transistors. The amount of current flowing through said plurality of MOS transistors generates an output voltage (V.sub.OUT) from the digital to analog converter of this invention. This output voltage may be positive or negative with respect to the reference voltage, thus the output voltage is bipolar.

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San Jose, CA, United States of America

Yusuf A Haque