Kabushiki Kaisha Toshiba

Yuso Udo

Hajime Nagano

Shinichi Nitta

Tsutomu Sato

Ichiro Mizushima

Takashi Yamada

Katsuya Okumura

Yukihiro Ushiku

Hiroaki Yamada

Soichi Nadahara

Masao Iwase

Hiroshi Matsushita

Tsunetoshi Arikado

Norihiko Tsuchiya

Junji Sugamoto

Katsujiro Tanzawa

Moriya Miyashita

A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them

A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer

A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.

A semiconductor wafer having an effective chip region set within an effective element region in which an element is formed and required for forming a single chip and an ineffective chip region which includes an ineffective element region in which no element is formed and required for forming a single chip. A degree of unevenness of a surface of the semiconductor wafer is measured at a plurality of sites within a predetermined region by an unevenness measuring section by applying light thereof, so that unevenness data are output. The predetermined region includes either or a part of both of the effective chip region and the ineffective chip region. A reference plane to which light is applied is determined by using only unevenness data of the effective chip region after unevenness data of the ineffective chip region are eliminated from the unevenness data. Inclination of the semiconductor wafer is controlled in accordance with the reference plane obtained through the calculation performed by the calculating section.

Pattern exposure apparatus for transferring circuit pattern on semiconductor wafer and pattern exposure method

Growing community of inventors

Tokyo, Japan

Yuso Udo