Taiwan Semiconductor Manufacturing Comp. Ltd.

Yushun Lin

Sung-Hui Huang

Shang-Yun Hou

Kuan-Yu Huang

Heh-Chang Huang

Chen-Hua Douglas Yu

Chi-Hsi Wu

Ying-Ching Shih

Hsien-Pin Hu

Hsing-Kuo Hsia

Chin-Fu Kao

Jui Hsieh Lai

Li-Chung Kuo

Wen-Hsin Wei

Tien-Yu Huang

Wen-Cheng Chen

Chih-Chieh Hung

Kung-Chen Yeh

Shu-Chia Hsu

Pai-Yuan Li

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.

Photonic package and method forming same

Method of forming a dummy die of an integrated circuit having an embedded annular structure

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.

Chip package structure with dummy bump and method for forming the same

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Taipei, Taiwan

Yushun Lin