Kabushiki Kaisha Toshiba

Yusei Itaya

Toshiyuki Furusawa

Masaru Ozeki

Masanori Kurata

Ryusuke Murakami

A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory ( ) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (m&times;n)-bits of a unit word length; two arithmetic operand storing registers ( ) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle ( ); and an arithmetic result storing register ( ) for storing the arithmetic results outputted by said arithmetic logical unit.

Digital arithmetic integrated circuit

A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit wiord length and the second arithmetic data string being composed of (m.times.n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.

An image processing system conducts a video effect processing. In the mosaic-image-processing, a dc component of inversely quantized discrete cosine transform (DCT) coefficients is multiplied by a constant h other than zero and an ac component of the inversely quantized DCT coefficients is replaced with zero. In the case of monochromatic-image-processing, a dc component D.sub.y of a luminance block Y of the inversely quantized DCT coefficients is multiplied by a constant i other than zero and an ac component A.sub.y of the luminance block Y is multiplied by a constant I other than zero, dc components D.sub.Cb and D.sub.Cr of chrominance blocks Cb and Cr of the inversely quantized DCT coefficients are replaced with constants j and k, respectively, and ac components A.sub.Cb and A.sub.Cr of the chrominance blocks Cb and Cr are replaced with constants J and K, respectively. In the thermographic-image processing, a dc component D.sub.y of the luminance block Y is processed into dc components D.sub.Cb '=mD.sub.y +n and D.sub.Cr '=pD.sub.y +q where m, n, p and q are a constant, respectively, ac component A.sub.y of the luminance block Y is processed into ac components A.sub.Cb '=MA.sub.y +N and A.sub.Cr '=PA.sub.y +Q where M, N, P and Q are a constant, respectively, and the dc component D.sub.y and the ac component A.sub.y are replaced with constants s and S, respectively.

Growing community of inventors

Yokohama, Japan

Yusei Itaya