Nvidia Corporation

Yury Y Uralsky

Henry Packard Moreton

Eric Brian Lum

Ziyad Sami Hakura

Dale L Kirkland

Jeffrey A Bolz

Patrick Richard Brown

Jerome Francis Duluk, Jr

Jonah Matthew Alben

Rui Manuel Bastos

Alexey Panteleev

Evgeny Makarov

Christoph Kubisch

Sergey Bolotov

Jack H Choquette

Steven James Heinrich

Rouslan Lyubomirov Dimitrov

Marco Salvi

Tyson J Bergland

Emmett Michael Kilgariff

John Matthew Burgess

Alexander Lev Minkin

Gregory Muthler

Magnus Andersson

Thomas A Petersen

Jonathan J Dunaisky

Pierre Boudier

Ankan Banerjee

Prakshep Mehta

Gregory Massal

Oleg Kuznetsov

Shirish C Gadre

Aaron Eliot Lefohn

Anjul Patney

Michael Alan Fetterman

Christopher Ryan Wyman

John F Spitzer

Rev Lebaredian

Stefano A Pescador

Eric Enderton

Kayvon Fatahalian

Lars Nordskog

Cyril Crassin

Cynthia Allison

Yong He

G Evan Hart, Jr

Nikhil Dixit

Yubo Zhang

Timo Oskari Aila

Tero Tapani Karras

Albert Meixner

James Leroy Deming

William P Newhall, Jr

Cass Watson Everitt

Andrew J Tao

Morgan McGuire

Christopher J Migdal

Walter Robert Steiner

Christian Amsinck

Poornachandra Rao

Justin Cobb

Anders M Kugler

Patrick James Neill

Lei Yang

Barry Nolan Rodgers

Dmitriy Zhdan

Mehmet Cem Cebenoyan

David Charles Patrick

Kirill A Dmitriev

Amanpreet Grewal

Cyril Jean-Francois Crassin

Ignacio Llamas Ubieto

Pemith Randima Fernando

Dmitry Zhdan

Levi Oliver

Johannes Deligiannis

Matthijs De Smedt

Alexey Barkovoy

Andrei S Tatarinov

Lup-Yen Peter Young

Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.

Accelerating triangle visibility tests for real-time ray tracing

A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.

Displaced micro-meshes for ray and path tracing

The present technology augments the GPU compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. A simple scheduling model based on scalar counters (e.g., semaphores) abstract the availability of hardware resources. Resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. Semantics of the counters/semaphores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.

Programming model for resource-constrained scheduling

In various embodiments, an encoded sequence (e.g., a compressed sequence for uncompressed data) that includes variable-length codes is decoded in an iterative fashion to generate a decoded sequence of symbols. During each iteration, a group of threads decode in parallel the codes in the encoded sequence to generate symbols. The group of threads then compute offsets based on the sizes of the symbols. Subsequently, the group of threads generates in parallel a contiguous portion of the decoded sequence based on the symbols, an output address, and the offsets.

Parallel decoding techniques

A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.

Enhanced anti-aliasing by varying sample patterns spatially and/or temporally

In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images. In operation, the parallel processor causes execution threads to execute a task shading program on an input mesh to generate a task shader output specifying a mesh shader count. The parallel processor then generates mesh shader identifiers, where the total number of the mesh shader identifiers equals the mesh shader count. For each mesh shader identifier, the parallel processor invokes a mesh shader based on the mesh shader identifier and the task shader output to generate geometry associated with the mesh shader identifier. Subsequently, the parallel processor performs operations on the geometries associated with the mesh shader identifiers to generate a rendered image. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.

Techniques for representing and processing geometry within an expanded graphics processing pipeline

In various embodiments, a deduplication application pre-processes index buffers for a graphics processing pipeline that generates rendered images via a shading program. In operation, the deduplication application causes execution threads to identify a set of unique vertices specified in an index buffer based on an instruction. The deduplication application then generates a vertex buffer and an indirect index buffer based on the set of unique vertices. The vertex buffer and the indirect index buffer are associated with a portion of an input mesh. The graphics processing pipeline then renders a first frame and a second frame based on the vertex buffer, the indirect index buffer, and the shading program. Advantageously, the graphics processing pipeline may re-use the vertex buffer and indirect index buffer until the topology of the input mesh changes.

Techniques for pre-processing index buffers for a graphics processing pipeline

A graphics processing pipeline includes three architectural features that allow a fragment shader to efficiently calculate per-sample attribute values using barycentric coordinates and per-vertex attributes. The first feature is barycentric coordinate injection to provide barycentric coordinates to the fragment shader. The second feature is an attribute qualifier that allows an attribute of a graphics primitive to be processed without conventional fixed-function interpolation. The third feature is a direct access path from the fragment shader to triangle data storage hardware resources where vertex attribute data and/or plane equation coefficients are stored. Allowing the fragment shader to calculate per-sample attribute values in this way advantageously increases system flexibility while reducing workload associated with triangle plane equation setup.

System-generated stable barycentric coordinates and direct plane equation access

A system, method, and computer program product are provided for simultaneously determining settings for a plurality of parameter variations. In use, a plurality of parameter variations associated with a device is identified. Additionally, settings for each of the plurality of parameter variations are determined simultaneously.

System, method, and computer program product for simultaneously determining settings for a plurality of parameter variations

Methods and apparatuses are disclosed for reporting texture footprint information. A texture footprint identifies the portion of a texture that will be utilized in rendering a pixel in a scene. The disclosed methods and apparatuses advantageously improve system efficiency in decoupled shading systems by first identifying which texels in a given texture map are needed for subsequently rendering a scene. Therefore, the number of texels that are generated and stored may be reduced to include the identified texels. Texels that are not identified need not be rendered and/or stored.

Method and apparatus for obtaining sampled positions of texturing operations

In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images via a shading program. In operation, the parallel processor causes a first set of execution threads to execute the shading program on a first portion of the input mesh to generate first geometry stored in an on-chip memory. The parallel processor also causes a second set of execution threads to execute the mesh shading program on a second portion of the input mesh to generate second geometry stored in the on-chip memory. Subsequently, the parallel processor reads the first geometry and the second geometry from the on-chip memory, and performs operations on the first geometry and the second geometry to generate a rendered image derived from the input mesh. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.

Techniques for representing and processing geometry within a graphics processing pipeline

A system for, and method of, computing reduced-resolution indirect illumination using interpolated directional incoming radiance and a graphics processing subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a cone tracing shader executable in a graphics processing unit to compute directional incoming radiance cones for sparse pixels and project the directional incoming radiance cones on a basis and (2) an interpolation shader executable in the graphics processing unit to compute outgoing radiance values for untraced pixels based on directional incoming radiance values for neighboring ones of the sparse pixels.

System and method for computing reduced-resolution indirect illumination using interpolated directional incoming radiance

Techniques for rendering images on multiple tilted displays concurrently to mitigate perspective distortion are disclosed herein. According to one described approach, viewports are assigned to a center monitor and two peripheral monitors. Scene data for the viewports is calculated, and geometric primitives are generated for the viewports based on the scene data. Image transformation is performed based on a modified perspective value to modify geometry of the geometric primitives based on tilt angles of the displays, and the geometric primitives are rasterized using the modified geometry.

Method and apparatus for rendering perspective-correct images for a tilted multi-display environment

Growing community of inventors

Santa Clara, CA, United States of America

Yury Y Uralsky