Ciena Corporation

Pmc-sierra, Inc.

Yuriy Greshishchev

Naim Ben-Hamida

Mahdi Parvizi

Douglas Stuart McPherson

Kim Bryon Roberts

Shahab Oveis Gharan

Sadok Aouini

Robert G Gibbins

Anna Sakharova

Larrie Simon Carr

Graeme Barclay Boyd

Ian B Betty

Aravinthan Vigneswaran

Ian Roberts

Douglas Mcpherson

Ian Betty

Described are broadband active coupling circuits and methods. A broadband active coupling circuit includes a high-pass circuit configured to provide a high frequency response for a broadband signal and a low-pass circuit connected in parallel with the high-pass circuit. The low-pass circuit is configured to provide a low frequency response for the broadband signal, where the low-pass circuit includes an active circuit configured to minimally impact the high frequency response provided by the high-pass circuit.

Broadband active coupling method and device

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F)(F/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Apparatus and methods for low power frequency clock generation and distribution

Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

Apparatus and methods for high frequency clock generation

An apparatus is configured to generate, from a stream of periodic digital samples, a first sub-stream of periodic analog samples and a second sub-stream of periodic analog samples, each sub-stream comprising substantially stable time intervals. The apparatus is further configured to generate a sign-modulated sub-stream by applying to the second sub-stream a sign modulation operation effecting a sign transition during a stable time interval of the second sub-stream. The apparatus is further configured to generate an output stream of periodic analog samples based on a sum of the first sub-stream and the sign-modulated sub-stream, wherein a period of the output stream is shorter than periods of the first and second sub-streams.

Digital-to-analog conversion with sign modulation

Described are apparatus and methods for low power clock generation in multi-channel high speed devices. In implementations, a multi-channel data processing device includes a low frequency clock generation and distribution circuit configured to generate and distribute a 1/N sampling frequency (F)(F/N) clock, wherein N is larger or equal to 8, and multiple data processing channels connected to the low frequency generation and distribution circuit. Each data processing channel including input ports associated with different operating frequency clocks, and a channel local clock generation circuit comprising multipliers associated with some of the input ports, each multiplier configured to multiply the F/N frequency clock to locally generate an operating frequency clock associated with an input port of the input ports.

Apparatus and methods for low power clock generation in multi-channel high speed devices

A controlled switch having N inputs and a single output (N&#x2265;2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

Digital-to-analog converter and generation of high-bandwidth analog signals

Described herein are apparatus and methods for realization of time interleaved digital-to-analog converters (DACs) by detecting and aligning phase mismatches. In an implementation, a N-time interleaved DAC includes N DACs and N replica DACs, where a first set of N/2 DACs operate at a clock A and a second set of N/2 DACs operate at a clock B, and where N is at least two. The phase detector generates a phase detection output by comparing outputs of the first and second set of N/2 replica DACs with a multiplexor (MUX) clock, where the MUX clock is a multiple of a frequency of the clock A or the clock B. The clock A and the clock B are aligned with the MUX clock by advancing a phase of the clock A and the clock B until the phase detection output achieves a zero crossing.

Apparatus and methods for realization of N time interleaved digital-to-analog converters

A controlled switch having N inputs and a single output (N&#x2265;2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields the high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

A coherent optical receiver Includes an electro-optic module coupled to an electronic signal processing Integrated circuit (IC) via a parallel analog transmission line bus. The electro-optic module receives and detects an optical channel light including a high-bandwidth signal modulated thereon. The electro-optic module includes: a single optical hybrid for mixing the optical channel light with a corresponding continuous wave local oscillator light to generate a mixed light containing the high-bandwidth data signal, at least one photodetector; and an analog frequency decimator for generating a set of parallel analog signals, each analog signal representing a respective portion of the high-bandwidth signal. The electronic signal processing IC includes a respective Analog-to-digital (A/D) converter for sampling each one of the set of parallel analog signals, and for generating corresponding parallel digital sample streams; and a digital signal processor (DSP) for processing the parallel digital sample streams to extract the high-bandwidth signal.

Parallel conversion between optical and digital

Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.

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Ottawa, Canada

Yuriy Greshishchev