Panasonic Holdings Corporation

Panasonic Corporation

Yuriko Hayata

Kazuyuki Kouno

Takashi Ono

Masayoshi Nakayama

Reiji Mochida

Hitoshi Suwa

A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Neural network computation circuit including non-volatile semiconductor memory element

A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.

Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.

Neural network computation circuit including semiconductor memory element, and method of operation

A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.

Neural network computation circuit including semiconductor storage elements

A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.

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Osaka, Japan

Yuriko Hayata